Полупроводники. Каталог (2011 год)

1/16

L6562

November 2005

Features

■

REALISED IN BCD TECHNOLOGY

■

TRANSITION-MODE CONTROL OF PFC PRE-
REGULATORS

■

PROPRIETARY MULTIPLIER DESIGN FOR
MINIMUM THD OF AC INPUT CURRENT

■

VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION

■

ULTRA-LOW (

≤

A) START-UP CURRENT

■

LOW (

≤

4 mA) QUIESCENT CURRENT

■

EXTENDED IC SUPPLY VOLTAGE RANGE

■

ON-CHIP FILTER ON CURRENT SENSE

■

DISABLE FUNCTION

■

1% (@ Tj = 25 °C) INTERNAL REFERENCE
VOLTAGE

■

-600/+800mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN AND VOLTAGE CLAMP

■

DIP-8/SO-8 PACKAGES ECOPACK

1.1 APPLICATIONS

■

PFC PRE-REGULATORS FOR:

– IEC61000-3-2 COMPLIANT SMPS (TV,

DESKTOP PC, MONITOR) UP TO 300W

– HI-END AC-DC ADAPTER/CHARGER
– ENTRY LEVEL SERVER & WEB SERVER

Description

The L6562 is a current-mode PFC controller oper-
ating in Transition Mode (TM). Pin-to-pin compati-
ble with the predecessor L6561, it offers improved
performance.

TRANSITION-MODE PFC CONTROLLER

Figure 2. Block Diagram

MULTIPLIER AND

THD OPTIMIZER

REF2

OVERVOLTAGE

DETECTION

VOLTAGE

REGULATOR

UVLO

INTERNAL

SUPPLY 7V

2.5V

DRIVER

STARTER

ZERO CURRENT

DETECTOR

DISABLE

2.1 V
1.6 V

ZCD

INV

COMP

MULT

GND

25 V

40K

5pF

15 V

Starter

stop

Rev. 8

Figure 1. Packages

Table 1. Order Codes

Part Number

Package

L6562N

DIP-8

L6562D

SO-8

L6562DTR

Tape & Reel

DIP-8

SO-8

L6562

2/16

2 Description

(continued)

The highly linear multiplier includes a special circuit, able to reduce AC input current distortion, that allows
wide-range-mains operation with an extremely low THD, even over a large load range.

The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1% @Tj =
25°C) internal voltage reference.

The device features extremely low consumption (

≤

A before start-up and <4 mA running) and includes

a disable function suitable for IC remote ON/OFF, which makes it easier to comply with energy saving
norms (Blue Angel, EnergyStar, Energy2000, etc.).

An effective two-step OVP enables to safely handle overvoltages either occurring at start-up or resulting
from load disconnection.

The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS-
FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solu-
tion for EN61000-3-2 compliant SMPS's up to 300W.

Table 2. Absolute Maximum Ratings

Figure 3. Pin Connection

(Top view)

Table 3. Thermal Data

Symbol

Pin

Parameter

Value

Unit

IC Supply voltage (Icc = 20 mA)

self-limited

---

1 to 4

Analog Inputs & Outputs

-0.3 to 8

IZCD

Zero Current Detector Max. Current

-50 (source)

10 (sink)

tot

Power Dissipation @Tamb = 50°C (DIP-8)

(SO-8)

0.65

Junction Temperature Operating range

-40 to 150

°C

stg

Storage Temperature

-55 to 150

°C

Symbol

Parameter

SO8

Minidip

Unit

th j-amb

Max. Thermal Resistance, Junction-to-ambient

150

100

°C/W

ZCD

INV

COMP

MULT

Vcc

GND

3/16

L6562

Table 4. Pin Description

N°

Pin

Function

INV

Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.

COMP

Output of the error amplifier. A compensation network is placed between this pin and INV (pin
#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.

MULT

Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop.

Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped
reference, generated by the multiplier, to determine MOSFET’s turn-off.

ZCD

Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET’s turn-on.

GND

Ground. Current return for both the signal part of the IC and the gate driver.

Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high
Vcc.

Vcc

Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper
limit is extended to 22V min. to provide more headroom for supply voltage changes.

Table 5. Electrical Characteristics

= -25 to 125°C, V

= 12, C

= 1 nF; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SUPPLY VOLTAGE

Operating range

After turn-on

10.3

CCon

Turn-on threshold

(1)

CCOff

Turn-off threshold

(1)

8.7

9.5

10.3

Hys

Hysteresis

2.2

2.8

Zener Voltage

= 20 mA

SUPPLY CURRENT

start-up

Start-up Current

Before turn-on, V

=11V

µA

Quiescent Current

After turn-on

2.5

3.75

Operating Supply Current

@ 70 kHz

3.5

Quiescent Current

During OVP (either static or
dynamic) or V

ZCD

=150 mV

2.2

MULTIPLIER INPUT

MULT

Input Bias Current

VFF

= 0 to 4 V

-1

µA

MULT

Linear Operation Range

0 to 3

Output Max. Slope

MULT

= 0 to 0.5V

COMP

= Upper clamp

1.65

1.9

V/V

Gain

(2)

MULT

= 1 V, V

COMP

= 4 V

0.5

0.6

0.7

1/V

ERROR AMPLIFIER

INV

Voltage Feedback Input
Threshold

= 25 °C

2.465

2.5

2.535

10.3 V < Vcc < 22 V

(1)

2.44

2.56

Line Regulation

Vcc = 10.3 V to 22V

INV

Input Bias Current

INV

= 0 to 3 V

-1

µA

C S

∆

MU L T

∆

---------------------

L6562

4/16

(1)

All parameters are in tracking

(2)

The multiplier output is given by:

(3)

Parameters guaranteed by design, functionality tested in production.

Voltage Gain

Open loop

Gain-Bandwidth Product

MHz

COMP

Source Current

COMP

= 4V, V

INV

= 2.4 V

-2

-3.5

-5

Sink Current

COMP

= 4V, V

INV

= 2.6 V

2.5

4.5

COMP

Upper Clamp Voltage

SOURCE

= 0.5 mA

5.3

5.7

Lower Clamp Voltage

SINK

= 0.5 mA

(1)

2.1

2.25

2.4

CURRENT SENSE COMPARATOR

Input Bias Current

= 0

-1

µA

d(H-L)

Delay to Outpu

200

350

CS clamp

Current sense reference clamp

COMP

= Upper clamp

1.6

1.7

1.8

CSoffset

Current sense offset

MULT

= 0

MULT

= 2.5V

ZERO CURRENT DETECTOR

ZCDH

Upper Clamp Voltage

ZCD

= 2.5 mA

5.0

5.7

6.5

ZCDL

Lower Clamp Voltage

ZCD

= -2.5 mA

0.3

0.65

ZCDA

Arming Voltage
(positive-going edge)

(3)

2.1

ZCDT

Triggering Voltage
(negative-going edge)

(3)

1.6

ZCDb

Input Bias Current

ZCD

= 1 to 4.5 V

µA

ZCDsrc

Source Current Capability

-2.5

-5.5

ZCDsnk

Sink Current Capability

2.5

ZCDdis

Disable threshold

150

200

250

ZCDen

Restart threshold

350

ZCDres

Restart Current after Disable

µA

STARTER

START

Start Timer period

130

300

µs

OUTPUT OVERVOLTAGE

OVP

Dynamic OVP triggering current

µA

Hys

Hysteresis

(3)

µA

Static OVP threshold

(1)

2.1

2.25

2.4

GATE DRIVER

Dropout Voltage

GDsource

= 20 mA

2.6

GDsource

= 200 mA

2.5

GDsink

= 200 mA

0.9

1.9

Voltage Fall Time

Voltage Rise Time

Oclamp

Output clamp voltage

GDsource

= 5mA; Vcc = 20V

UVLO saturation

= 0 to V

CCon

, I

sink

=10mA

1.1

Table 5. Electrical Characteristics

(continued)

= -25 to 125°C, V

= 12, C

= 1 nF; unless otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

c s

K V

M U L T

C O M P

2.5

–

(

)

⋅

5/16

L6562

Typical Electrical Characteristics

Figure 4. Supply current vs. Supply voltage

Figure 5. Start-up & UVLO vs. T

Figure 6. IC consumption vs. T

Figure 7. Vcc Zener voltage vs. T

Vcc(V)

0.005

0.01

0.05

0.1

0.5

(mA)

Co = 1nF

f = 70 kHz

= 25°C

Tj (°C)

CC-ON

(V)

CC-OFF

(V)

-50

100

150

9.5

10.5

11.5

12.5

-50

100

150

0.02

0.05

0.1

0.2

0.5

Icc

[mA]

Operating

Quiescent

Disabled or

during OVP

Before start-up

Vcc = 12 V

Co = 1 nF

f = 70 kHz

Tj (°C)

Vcc

(V)

-50

100

150

L6562

6/16

Figure 8. Feedback reference vs. T

Figure 9. OVP current vs. T

Figure 10. E/A output clamp levels vs. T

Figure 11. Delay-to-output vs. T

Figure 12. Multiplier characteristic

Figure 13. Multiplier gain vs. T

REF

(V)

-50

100

150

2.4

2.45

2.5

2.55

2.6

Vcc = 12 V

Tj (°C)

OVP

(µA)

-50

100

150

39.5

40.5

Vcc = 12 V

Tj (°C)

Vpin2

(V)

-50

100

150

Upper clamp

Lower clamp

Vcc = 12 V

Tj (°C)

D(H-L)

(ns)

-50

100

150

100

200

300

400

500

Vcc = 12 V

MULT

(pin 3) (V)

COMP

(pin 2)

(V)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

(pin 4)

2.6

3.0

3.2

5.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

(V)

4.0

2.8

upper voltage
clamp

3.5

Tj (°C)

-50

100

150

0.2

0.4

0.6

0.8

Vcc = 12 V

COMP

=4 V

MULT

=1V

7/16

L6562

Figure 14. Vcs clamp vs. T

Figure 15. Start-up timer vs. T

Figure 16. ZCD clamp levels vs. T

Figure 17. ZCD source capability vs. T

Figure 18. Gate-drive output low saturation

Figure 19. Gate-drive output high saturation

Tj (°C)

CSx

(V)

-50

100

150

1.2

1.4

1.6

1.8

Vcc = 12 V

COMP

= Upper clamp

Tj (°C)

Tstart

(µs)

-50

100

150

100

110

120

130

140

150

Vcc = 12 V

Tj (°C)

ZCD

(V)

-50

100

150

Vcc = 12 V

ZCD

= ±2.5 mA

Upper clamp

Lower clamp

Tj (°C)

ZCDsrc

(mA)

-50

100

150

-8

-6

-4

-2

Vcc = 12 V

ZCD

= lower clamp

pin7

[V]

200

400

600

800

1,000

[mA]

Tj = 25 °C

Vcc = 11 V

SINK

100

200

300

400

500

600

700

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

pin7

[V]

[mA]

Tj = 25 °C

Vcc = 11 V

SOURCE

Vcc - 2.0

Vcc - 2.5

Vcc - 3.0

Vcc - 3.5

Vcc - 4.0

L6562

8/16

Figure 20. Gate-drive clamp vs. T

Figure 21. UVLO saturation vs. T

Tj (°C)

Vpin7

clamp

(V)

-50

100

150

Vcc = 20 V

Tj (°C)

-50

100

150

0.5

0.6

0.7

0.8

0.9

1.1

Vcc = 0 V

Vpin7

(V)

Application Information

4.1 Overvoltage protection

Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator
close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo-
nents, the current through R1, I

, equals that through R2, I

. Considering that the non-inverting input of

the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:

If the output voltage experiences an abrupt change

∆

Vo > 0 due to a load drop, the voltage at pin INV will

be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant to achieve high PF (this is why

∆

Vo can be large). As a result,

the current through R2 will remain equal to 2.5/R2 but that through R1 will become:

The difference current

∆

=I'

-I

=I'

-I

∆

Vo/R1 will flow through the compensation network and en-

ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about
37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv-
ered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is
forced low to switch off the external power transistor and the IC put in an idle state. This condition is main-
tained until the current falls below approximately 10 µA, which re-enables the internal starter and allows
switching to restart. The output

∆

Vo that is able to trigger the Dynamic OVP function is then:

An important advantage of this technique is that the OV level can be set independently of the regulated
output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another
advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on

∆

Vo.

Since

∆

Vo << Vo, the tolerance on the absolute value will be proportionally reduced.

Example: Vo = 400 V,

∆

Vo = 40 V. Then: R1=40V/40

A=1M

Ω

; R2=1M

Ω

·2.5/(400-2.5)=6.289k

Ω

. The tol-

erance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value.

2.5
R2

--------

2.5

–

----------------------

2.5

–

∆

R 1

----------------------------------------

∆

R 1 40 10

–

⋅

9/16

L6562

When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nom-
inal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier out-
put will saturate low; hence, when this is detected, the external power transistor is switched off and the IC
put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its lin-
ear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low.

When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge
of the Vcc capacitor and increase the hold-up capability of the IC supply system.

4.2 THD optimizer circuit

The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC
input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total
Harmonic Distortion) of the current is considerably reduced.

A major cause of this distortion is the inability of the system to transfer energy effectively when the instan-
taneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after
the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be
reverse-biased and the input current flow to temporarily stop.

Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)

To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more
energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will
result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-
frequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key
waveforms of a standard TM PFC controller are compared to those of the L6562.

Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to

Imains

Vdrain

Imains

Vdrain

Input current

MOSFET's drain voltage

Rectified mains voltage

Input current

L6562

10/16

the output of the multiplier in the proximity of the line voltage zero-crossings. This offset is reduced as the
instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the
top of the sinusoid.

To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after the bridge rec-
tifier should be minimized, compatibly with EMI filtering needs. A large capacitance, in fact, introduces a
conduction dead-angle of the AC input current in itself - even with an ideal energy transfer by the PFC pre-
regulator - thus making the action of the optimizer circuit little effective.

Figure 23. Typical application circuit (250W, Wide-range mains)

Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic

NTC

2.5

Ω

BRIDGE

STBR606

1.5 M

Ω

1 µF

400V

22 k

Ω

C29

22 µF

25V

FUSE

5A/250V

180 k

Ω

1N4150

1N5248B

R14

100

Ω

C5 12 nF

68 k

Ω

L6562

Ω

MOS

STP12NM50

7 °C/W heat sink

R11

750 k

Ω

100 µF

450V

Vo=400V

Po=250W

Vac

(85V to 265V)

0.33

Ω

R13

9.53 k

Ω

100 nF

10nF

STTH5L06

R50 10 k

Ω

C3 2.2 µF

1.5 M

Ω

180 k

Ω

R10

0.33

Ω

R12

750 k

Ω

C23

680 nF

Boost Inductor Spec: EB0057-C (

COILCRAFT

)

D3 1N5406

NTC

2.5

Ω

BRIDGE

DF06M

750 k

Ω

0.47 µF

400V

10 k

Ω

C29

22 µF

25V

FUSE

4A/250V

180 k

Ω

1N4150

1N5248B

R14

100

Ω

C5 12 nF

68 k

Ω

L6562

Ω

MOS

STP8NM50

R11

750 k

Ω

47 µF

450V

Vo=400V

Po=80W

Vac

(85V to 265V)

0.82

Ω

0.6 W

R13

9.53 k

Ω

100 nF

10nF

STTH1L06

R50 12 k

Ω

C3 680 nF

750 k

Ω

180 k

Ω

R10

0.82

Ω

0.6 W

R12

750 k

Ω

C23

330 nF

Boost Inductor Spec (ITACOIL E2543/E)

E25x13x7 core, 3C85 ferrite
1.5 mm gap for 0.7 mH primary inductance
Primary: 105 turns 20x0.1 mm
Secondary: 11 turns 0.1 mm

11/16

L6562

Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm)

Table 6. EVAL6562N: Evaluation results at full load

Table 7. EVAL6562N: Evaluation results at half load

Vin (V

)

Pin (W)

Vo (V

)

∆

Vo(V

pk-pk

)

Po (W)

(%)

THD (%)

86.4

394.79

12.8

80.16

92.8

0.998

3.6

110

84.6

394.86

12.8

80.20

94.8

0.996

4.2

135

83.8

394.86

12.8

80.20

95.7

0.991

4.9

175

83.2

394.87

15.5

80.20

96.4

0.981

6.5

220

82.9

394.87

15.7

80.20

96.7

0.956

7.8

265

82.7

394.87

15.9

80.20

97.0

0.915

9.2

Note: measurements done with the line filter shown in figure 23

Vin (V

)

Pin (W)

Vo (V

)

∆

Vo(V

pk-pk

)

Po (W)

(%)

THD (%)

42.8

394.86

6.6

40.20

93.9

0.994

5.5

110

42.5

394.90

6.6

40.20

94.6

0.985

6.2

135

42.5

394.91

6.7

40.20

94.6

0.967

7.1

175

42.5

394.93

8.0

40.19

94.6

0.939

8.3

220

42.6

394.94

8.2

40.19

94.3

0.869

9.8

265

42.6

394.94

8.3

40.19

94.3

0.776

11.4

Note: measurements done with the line filter shown in figure 23

L6562

12/16

Table 8. EVAL6562N: No-load measurements

Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation

Vin (V

)

Pin (W)

Vo (V

)

∆

Vo(V

pk-pk

)

Po (W)

0.4

396.77

0.45

110

0.3

396.82

0.55

135

0.3

396.83

0.60

175

(*)

0.4

396.90

1.00

220

(*)

0.4

396.95

1.40

265

(*)

0.5

396.98

1.65

(*)

Vcc = 12V supplied externally

to the AC

source

B82732

47 mH, 1.3A

EPCOS

B81133

470 nF, X2

EPCOS

EVAL6562N

B81133

680 nF, X2

EPCOS

13/16

L6562

Package Information

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These

packages have a Lead-free second level interconnect. The category of second Level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 27. DIP-8 Mechanical Data & Package Dimensions

OUTLINE AND

MECHANICAL DATA

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

3.32

0.131

0.51

0.020

1.15

1.65

0.045

0.065

0.356

0.55

0.014

0.022

0.204

0.304

0.008

0.012

10.92

0.430

7.95

9.75

0.313

0.384

2.54

0.100

7.62

0.300

7.62

0.300

6.6

0.260

5.08

0.200

3.18

3.81

0.125

0.150

1.52

0.060

DIP-8

L6562

14/16

Figure 28. SO-8 Mechanical Data & Package Dimensions

OUTLINE AND

MECHANICAL DATA

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

1.35

1.75

0.053

0.069

0.10

0.25

0.004

0.010

1.10

1.65

0.043

0.065

0.33

0.51

0.013

0.020

0.19

0.25

0.007

0.010

(1)

4.80

5.00

0.189

0.197

3.80

4.00

0.15

0.157

1.27

0.050

5.80

6.20

0.228

0.244

0.25

0.50

0.010

0.020

0.40

1.27

0.016

0.050

0˚ (min.), 8˚ (max.)

ddd

0.10

0.004

Note:

(1) Dimensions D does not include mold flash, protru-

sions or gate burrs.
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).

SO-8

0016023 C

Полупроводники. Каталог (2011 год) - часть 3