Content .. 4 5 6 7 ..

High Level Assembler for z/OS & z/VM & z/VSE. Language Reference (Version 1 Release 6) - page 6

Table 9. Alternative mnemonics for some branch relative instructions (continued)

Instruction

Alternative

Description

BRCT

JCT

Branch Relative on Count

BRCTG

JCTG

Branch Relative on Count

BRXH

JXH

Branch Relative on Index High

BRXHG

JXHG

Branch Relative on Index High

BRXLE

JXLE

Branch Rel. on Index Low or Equal

BRXLG

JXLEG

Branch Rel. on Index Low or Equal

Extended mnemonics are also provided for some machine instructions that are not

branches. These extended mnemonics can be used to represent alternative names

for the same instruction or for easy reference to useful cases where particular

values are used for masks or immediate values in the base instruction. All

extended mnemonics are documented with their corresponding base instructions in

z/Architecture Principles of Operation (SA22-7832).

Statement formats

Machine instructions are assembled into 2, 4, or 6 bytes of object code according to

the format of each instruction. Machine instruction formats include the following

(ordered by length attribute):

Length Attribute

Basic Formats

RI, RS, RSI, RX, SI

See the z/Architecture Principles of Operation information. for complete details about

machine instruction formats. See also “Examples of coded machine instructions” on

page 88.

When you code machine instructions, you use symbolic formats that correspond to

the actual machine language formats. Within each basic format, you can also code

variations of the symbolic representation, divided into groups according to the

basic formats shown in “Examples of coded machine instructions” on page 88.

The assembler converts only the operation code and the operand entries of the

assembler language statement into object code. The assembler assigns to a name

entry symbol the value of the address of the first byte of the assembled instruction.

When you use this same symbol in the operand of an assembler language

statement, the assembler uses this address value in converting the symbolic

operand into its object code form. The length attribute assigned to the symbol

depends on the basic machine language format of the instruction in which the

symbol appears as a name entry.

A remarks entry is not converted into object code.

An example of a typical assembler language statement follows:

LABEL

4,256(5,10)

LOAD INTO REG4

where:

LABEL Is the name entry

Chapter 4. Machine instruction statements

Is the operation code mnemonic (converted to hex 58)

Is the register operand (converted to hex 4)

256(5,10)

Are the storage operand entries (converted to hex 5A100)

LOAD INTO REG4

Are remarks not converted into object code

The object code of the assembled instruction, in hexadecimal, is:

5845A100 (4 bytes in RX format)

Symbolic operation codes

You must specify an operation code for each machine instruction statement. The

symbolic operation code, or mnemonic code as it is also called, indicates the type

of operation to be done; for example, A indicates the addition operation. Refer to

the z/Architecture Principles of Operation information for a complete list of symbolic

operation codes and the formats of the corresponding machine instructions.

The general format of the machine instruction operation code is:

Operation code format

►► VERB

►◄

MODIFIER

DATA TYPE

MACHINE FORMAT

Verb The verb must always be present. It typically consists of one or two

characters and specifies the operation to be done. The verb is underscored

in the following examples:

3,AREA

A indicates an add operation

MVC

TO,FROM

MV indicates a move operation

The other items in the operation code are not always present. They include the

following (underscores are used to indicate modifiers, data types, and machine

formats in the following examples):

Modifier

Modifier, which further defines the operation:

3,AREA

L indicates a logical operation

Data Type

Type qualifier, which indicates the type of data used by the instruction in

its operation:

CVB 3,BINAREA

B indicates binary data

MVC TO,FROM

C indicates character data

2,FLTSHRT

E indicates normalized short

floating-point data

2,FLTLONG

D indicates normalized long

floating-point data

Machine Format

Format qualifier, R indicating a register operand, or I indicating an

immediate operand. For example:

HLASM V1R6 Language Reference

ADR 2,4

R indicates a register operand

MVI FIELD,X’A1’

I indicates an immediate operand

AHI 7,123

Operand entries

Specify one or more operands in each machine instruction statement to provide the

data or the location of the data upon which the machine operation is to be done.

The operand entries consist of one or more fields or subfields, depending on the

format of the instruction being coded. They can specify a register, an address, a

length, or immediate data. You can omit length fields or subfields, which the

assembler computes for you from the other operand entries. You can code an

operand entry either with symbols or with self-defining terms.

The rules for coding operand entries are:

v A comma must separate operands.

v Parentheses must enclose subfields.

v A comma must separate subfields enclosed in parentheses.

v If a subfield is omitted because it is implicit in a symbolic address, the

parentheses that enclosed the subfield must be omitted.

v If two subfields are enclosed in parentheses and separated by commas, the

following applies:

- If both subfields are omitted because they are implicit in a symbolic entry, the

separating comma and the parentheses that were needed must also be

omitted.

- If the first subfield is omitted, the comma that separates it from the second

subfield must be written, as well as the enclosing parentheses.

- If the second subfield is omitted, the comma that separates it from the first

subfield must be omitted; however, the enclosing parentheses must be

written.

v Spaces must not appear within the operand field, except as part of a character

self-defining term, or in the specification of a character literal.

Registers

You can specify a register in an operand for use as an arithmetic accumulator, a

base register, an index register, and as a general depository for data to which you

want to refer repeatedly.

You must be careful when specifying a register whose contents have been affected

by the execution of another machine instruction, the control program, or an

IBM-supplied system macro instruction.

For some machine instructions, you are limited in which registers you can specify

in an operand.

The expressions used to specify registers must have absolute values; in general,

registers 0 through 15 can be specified for machine instructions. However, the

following restrictions on register usage apply:

v The even-numbered registers must be specified for the following groups of

instructions:

- The double-shift instructions

- Most multiply and divide instructions

- The move long and compare logical long instructions

Chapter 4. Machine instruction statements

v If the NOAFPR ACONTROL operand is specified, then only the floating-point

registers (0, 2, 4, or 6) can be specified for floating-point instructions.

v If the AFPR ACONTROL operand is specified, then one of the floating-point

registers 0, 1, 4, 5, 8, 9, 12, or 13 can be specified for the instructions that use

extended floating-point data in pairs of registers, such as AXR, SXR, LTXBR, and

SQEBR.

v If the NOAFPR ACONTROL operand is specified, then either floating-point

The assembler checks the registers specified in the instruction statements of the

above groups. If the specified register does not comply with the stated restrictions,

the assembler issues a diagnostic message and does not assemble the instruction.

Binary zeros are generated in place of the machine code.

Registers that are not explicitly coded in symbolic assembler language

representation of machine instructions, but are nevertheless used by assembled

machine instructions, are divided into two categories:

Base registers that are implicit in the symbolic addresses specified. (See

“Addresses as machine instruction operands” on page 85.) The registers can be

identified by examining the object code or the USING instructions that assign

base registers for the source module.

Registers that are used by machine instructions, but do not appear in assembled

object code.

For double shift and fullword multiply and divide instructions, the

odd-numbered register, whose number is one greater than the even-numbered

For Move Long and Compare Logical Long instructions, the odd-numbered

registers, whose number is one greater than even-numbered registers

specified in the two operands.

For Branch on Index High (BXH) and the Branch on Index Low or Equal

(BXLE) instructions, if the register specified for the second operand is an

even-numbered register, the next higher odd-numbered register is used to

contain the value to be used for comparison.

For Load Multiple (LM, LAM) and Store Multiple (STM, STAM) instructions,

the registers that lie between the registers specified in the first two operands.

For extended-precision floating point instructions, the second register of the

For Compare and Form Codeword (CFC) instruction, registers 1, 2, and 3 are

used.

For Translate and Test (TRT) instruction, registers 1 and 2 are used.

–

For Update Tree (UPT) instruction, registers 0-5 are used.

–

For Edit and Mark (EDMK) instruction, register 1 is used.

–

For certain control instructions, one or more of registers 0-4 and register 14

are used. See “Control Instructions” in the z/Architecture Principles of Operation,

SA22-7832.

For certain input and output instructions, either or both registers 1 and 2 are

used. See “Input/Output Instructions” in the z/Architecture Principles of

Operation, SA22-7832.

The “General Purpose Register cross reference” in the HLASM Programmer's

Guide list registers are references to them, including those that do not appear

in the object code.

HLASM V1R6 Language Reference

The programming interface of the system control programs uses registers 0, 1, 13,

14, and 15.

Addresses as machine instruction operands

You can code a symbol in the name field of a machine instruction statement to

represent the address of that instruction. You can then refer to the symbol in the

operands of other machine instruction statements. The object code requires that

addresses be assembled in a numeric relative-offset or base-displacement format.

This format lets you specify addresses that are relocatable or absolute. Chapter 3,

“Program structures and addressing,” on page 51 describes how you use symbolic

addresses to refer to data in your assembler language program.

Defining Symbolic Addresses: Define relocatable addresses by either using a

symbol as the label in the name field of an assembler language statement, or

equating a symbol to a relocatable expression.

Define absolute addresses (or values) by equating a symbol to an absolute

expression.

Referring to Addresses: You can refer to relocatable and absolute addresses in the

operands of machine instruction statements. (Such address references are also

called addresses in this manual.) The two ways of coding addresses are:

v Implicitly—in a form that the assembler must first convert into an explicit

relative-offset or base-displacement form before it can be assembled into object

code.

v Explicitly—in a form that can be directly assembled into object code.

Implicit address

An implicit address is specified by coding one expression. The expression can be

relocatable or absolute. The assembler converts all implicit addresses into their

relative-offset or base-displacement form before it assembles them into object code.

The assembler cannot convert implicit addresses into explicit base-displacement

addresses unless a USING instruction has been specified, or for small absolute

expressions, where the address is resolved without a USING. The USING

instruction assigns both a base address, from which the assembler computes

displacements, and a base register, which is assumed to contain the base address.

The base register must be loaded with the correct base address at execution time.

For more information, refer to “Addressing” on page 64.

Explicit address

An explicit address is specified by coding two absolute expressions as follows:

v The first is an absolute expression for the displacement, whose value must lie in

the range 0 through 4095 (4095 is the maximum value that can be represented by

the 12 binary bits available for the displacement in the object code), or in the

range -524,288 to 524,287 for long-displacement instructions.

v The second (enclosed in parentheses) is an absolute expression for the base

An explicit base register designation must not accompany an implicit address.

However, in RX-format instructions, an index register can be coded with an

implicit address as well as with an explicit address. When two addresses are

required, each address can be coded as an explicit address or as an implicit

address.

Chapter 4. Machine instruction statements

Relative address

A relative address is specified by coding one expression. The expression is

relocatable or absolute. If a relocatable expression is used, then the assembler

converts the value to a signed number of halfwords relative to the current location

counter, and then uses that value in the object code. An absolute value can be used

for a relative address, but the assembler issues a warning message, as it uses the

supplied value, and this might cause unpredictable results.

Relocatability of addresses

There are two different types of address expression:

v An address expression that has a fixed value, independent of run-time

considerations such as where the program is located in memory, is called an

absolute address expression.

v An address expression with a value that depends on run-time considerations is

called a relocatable address expression. A relocatable expression with a value that

depends only on where a single control section is located in memory is called

simply relocatable. A relocatable expression with a value that depends other

run-time considerations is called complexly relocatable.

If the value of an address expression changes when the assumed origin of the

program is changed, and changes by the same amount, then the address is “simply

relocatable”. If the addressing expression does not change when the assumed

origin of the program is changed, then that address is “absolute”. If the addressing

expression changes by some other amount, the address is “complexly relocatable”.

Addresses in the relative-offset or base-displacement form are relocatable, because:

v Each relocatable address is assembled as a signed relative offset from the

instruction, or as a displacement from a base address and a base register.

v The base register contains the base address.

v If the object module assembled from your source module is relocated, only the

contents of the base register need reflect this relocation. This means that the

location in virtual storage of your base has changed, and that your base register

must contain this new base address.

v Addresses in your program have been assembled as relative to the base address;

therefore, the sum of the displacement and the contents of the base register point

to the correct address after relocation.

Absolute addresses are also assembled in the base-displacement form, but always

indicate a fixed location in virtual storage. This means that the contents of the base

Machine or object code format

Addresses assembled into the object code of machine instructions have the format

given in Figure 21 on page 87. Not all the instruction formats are shown in

Figure 21 on page 87.

The addresses represented have a value that is the sum of a displacement (see ▌1▐

in Figure 21 on page 87) and the contents of a base register (see ▌2▐ in Figure 21 on

page 87).

Index register: In RX-format instructions, the address represented has a value that

is the sum of a displacement, the contents of a base register, and the contents of an

index register (see ▌3▐ in Figure 21 on page 87).

HLASM V1R6 Language Reference

Format │ Coded or Symbolic │

Object Code

│ Representation of │

Representation

│ Explicit Address

│

of Addresses

───────┼───────────────────┼──────────────────────────────────────────────────────────────────────────────

│

│ │8 bits

│4

│12 bits

│4

│12 bits

│

│ │Operation

│bits │bits │bits │Displacement

│bits │Displacement

│

│ │Code

│

│Base │

│

│ │

│

│Reg. │

│

│ ├───────────┼─────┼─────┼─────┼─────────────────┼─────┼─────────────────┤

│

│ │

│

│ ▌2▐ │

▌1▐

│

│ │

│

⌂

│

⌂

│

│ ├ ─ ─ ─ ─ ─ ┼ ─ ─ ┼ ─ ─ ┼─────┼─────────────────┤

│

│ D₂(B₂)

│ │OP CODE

│ R₁ │ R₃ │ B₂ │

D₂

│

│ ├ ─ ─ ─ ─ ─ ┴ ─ ─ ┴ ─ ─ ┴─────┴─────────────────┤

│

│ │

┌──▌3▐ (Index Register)

│

│ │

⌂

│

│ ├ ─ ─ ─ ─ ─ ┬ ─ ─ ┬ ─ ─ ┬─────┬─────────────────┤

│

│ D₂(X₂,B₂)

│ │OP CODE

│ R₁ │ X₂ │ B₂ │

D₂

│

│ ├ ─ ─ ─ ─ ─ ┴ ─ ─ ┴ ─ ─ ┴─────┴─────────────────┤

│

│ │

│

│ │

│

│ ├ ─ ─ ─ ─ ─ ┬ ─ ─ ─ ─ ─ ┬─────┬─────────────────┤

│

│ D₁(B₁)

│ │OP CODE

│

I₂

│ B₁ │

D₁

│

│ ├ ─ ─ ─ ─ ─ ┴ ─ ─ ─ ─ ─ ┴─────┴─────────────────┤

│

│ │

│ ▌2▐ │

▌1▐

│

│ │

│

⌂

│

⌂

│

│ ├ ─ ─ ─ ─ ─ ┬ ─ ─ ─ ─ ─ ┬─────┬─────────────────┼─────┼─────────────────┤

│ D₁(,B₁),D₂(B₂)

│ │OP CODE

│

│ B₁ │

D₁

│ B₂ │

D₂

│

│ ├ ─ ─ ─ ─ ─ ┴ ─ ─ ─ ─ ─ ┴─────┴─────────────────┴─────┴─────────────────┤

I₂

Represents an immediate value

Represents a length

B₂, R₁, and R₃

Represent registers

Figure 21. Format of addresses in object code

Lengths

You can specify the length field in an SS-format instruction. This lets you indicate

explicitly the number of bytes of data at a virtual storage location that is to be

used by the instruction. However, you can often omit the length specification,

because the assembler computes an implicit length from the expression that

represents the address of the data. The assembler uses the implicit length as the

default.

See page “SS format” on page 95 for more information about SS-format

instructions.

Implicit Length

When a length subfield is omitted from an SS-format machine instruction,

an implicit length is assembled into the object code of the instruction. The

implicit length is either of the following:

v For an implicit address, it is the length attribute of the first or only term

in the expression representing the implicit address.

v For an explicit address, it is the length attribute of the first or only term in

the expression representing the displacement.

Chapter 4. Machine instruction statements

Explicit Length

When a length subfield is specified in an SS-format machine instruction,

the explicit length always overrides the implicit length.

An implicit or explicit length is the effective length. The length value

assembled is always one less than the effective length. If you want an

assembled length value of 0, an explicit length of 0 or 1 can be specified.

In the SS-format instructions requiring one length value, the allowable

range for explicit lengths is 0 through 256. In the SS-format instructions

requiring two length values, the allowable range for explicit lengths is 0

through 16.

Immediate data

In addition to registers, numeric values, relative addresses, and lengths, some

machine instruction operands require immediate data. Such data is assembled

directly into the object code of the machine instructions. Use immediate data to

specify the bit patterns for masks or other absolute values you need.

Specify immediate data only where it is required. Do not confuse it with address

references to constants and areas, or with any literals you specify as the operands

of machine instructions.

Immediate data must be specified as absolute expressions whose range of values

depends on the machine instruction for which the data is required. The immediate

data is assembled into its binary representation.

Examples of coded machine instructions

The examples that follow are grouped according to machine instruction format.

They show the various ways in which you can code the operands of machine

instructions. Both symbolic and numeric representation of fields and subfields are

shown in the examples. Therefore, assume that all symbols used are defined

elsewhere in the same source module.

The object code assembled from at least one coded statement per group is also

included. A complete summary of machine instruction formats with the coded

assembler language variants can be found in the z/Architecture Principles of

Operation, SA22-7832 (and also in the z/Architecture Reference Summary, SA22-7871).

These two documents provide the definitive reference to machine instruction

formats.

The examples that follow show the various instruction formats.

RI format

The operand fields of RI-format instructions designate a register and an immediate

operand, with the following exception:

v In BRC branching instructions, a 4 bit branching mask with a value 0 - 15

replaces the register designation.

Symbols used to represent registers (such as REG1 in the example) are assumed to

be equated to absolute values 0 - 15. The 16 bit immediate operand has two

different interpretations, depending on whether the instruction is a branching

instruction or not.

There are two types of non-branching RI-format instructions.

HLASM V1R6 Language Reference

v For most, the immediate value is treated as a signed binary integer (-32768

through +32767). This value can be specified by any absolute expression.

Op Code

OpCd

v For logical instructions such as TMH, the immediate field is a 16 bit mask.

Op Code

OpCd

Examples:

ALPHA1

AHI

REG1,2000

ALPHA2

MHI

3,1234

BETA1

TMH

7,X’8001’

When assembled, the object code for the instruction labeled BETA1, in

hexadecimal, is

A7708001

where:

A7.0

Is the operation code

Is register R₁

8001

Is the immediate data I2

For branching RI-format instructions, the immediate value is treated as a signed

binary integer representing the number of halfwords to branch relative to the

current location.

The branch target can be specified as a relocatable expression, in which case the

assembler performs some checking, and calculates the immediate value.

The branch target can also be specified as an absolute value, in which case the

assembler issues a warning before it assembles the instruction.

Examples:

ALPHA1

BRAS

1,BETA1

ALPHA2

BRC

3,ALPHA1

BETA1

BRCT

7,ALPHA1

When assembled, the object code for the instruction labeled BETA1, in

hexadecimal, is

A776FFFC

where:

A7.6

Is the operation code

Is register R₁

FFFC

Is the immediate data I2; a value of -4 decimal

If the GOFF assembler option is active, then it is possible to specify the target

address as an external symbol or an expression containing external symbols.

Chapter 4. Machine instruction statements

If an offset is specified it can be specified as an absolute or relocatable expression.

If the offset is specified as a relocatable expression, the assembler performs some

checking and calculates the immediate value. If the offset is an absolute expression

the assembler issues warning message ASMA056W.

Examples:

ALPHA1 BRAS

14,A-B+C+10

where A, B and C are external symbols

ALPHA2 BRASL

14,A-B+C+10

BETA1

BRC

15,A-B+C+10

When assembled, the object code for the instruction labeled BETA1, in

hexadecimal, is

A7F40005

where:

A7.4 is the operation code

is the condition code

0005 is the immediate data I2; a value of 5 decimal.

In addition GOFF Relocation Dictionary Data Items are generated for the external

symbols A, B, and C.

RR format

The operand fields of RR-format instructions designate two registers, with the

following exceptions:

v In BCR branching instructions, when a 4 bit branching mask replaces the first

v In SVC instructions, where an immediate value (0 - 255) replaces both registers

(see 200 in the instruction labeled DELTA1 in the examples).

Op Code

R₁

R₂

Symbols used to represent registers in RR-format instructions (see INDEX and REG2

in the instruction labeled ALPHA2 in the examples) are assumed to be equated to

absolute values 0 - 15.

Symbols used to represent immediate values in SVC instructions (see TEN in the

instruction labeled DELTA2 in the examples) are assumed to be equated to absolute

values 0 - 255.

Examples:

ALPHA1

1,2

ALPHA2

INDEX,REG2

GAMMA1

BCR

8,12

DELTA1

SVC

200

DELTA2

SVC

TEN

When assembled, the object code of the instruction labeled ALPHA1, in hexadecimal,

is:

1812

where:

HLASM V1R6 Language Reference

Is the operation code

Is register R₁

Is register R₂

RS format

The operand fields of RS-format instructions designate two registers, and a virtual

storage address (coded as an implicit address or an explicit address).

Op Code

R₃

In the Insert Characters under Mask (ICM) and the Store Characters under Mask

(STCM) instructions, a 4 bit mask, with a value 0 through 15, replaces the second

Op Code

M₃

Symbols used to represent registers (see REG4, REG6, and BASE in the instruction

labeled ALPHA2 in the examples) are assumed to be equated to absolute values 0 -

15.

Symbols used to represent implicit addresses (see AREA and IMPLICIT in the

instructions labeled BETA1 and DELTA2 in the examples) can be either relocatable or

absolute.

Symbols used to represent displacements (see DISPL in the instruction labeled

BETA2 in the examples) in explicit addresses are assumed to be equated to absolute

values 0 - 4095.

Examples

Chapter 4. Machine instruction statements

Sample Program - LRSAMP06 - HLASM

Page

Active

Usings: None

Loc

Object Code

Addr1

Addr2

Stmt

Source Statement

HLASM R6.0

2015/02/26 18.53

***********************************************************************

* Licensed Materials - Property of IBM

5696-234

* US Government Users Restricted Rights - Use, duplication

* or disclosure restricted by GSA ADP Schedule Contract

* with IBM Corp.

***********************************************************************

00000000

00000030

LPSAMP06 CSECT

00000003

EQU

00000004

EQU

00000006

EQU

0000000C

R12

EQU

0000000E

R14

EQU

0000000F

R15

EQU

0000000C

BASE

EQU

R:C 00000000

USING LPSAMP06,BASE Assign the base register

00000000

18CF

LR R12,R15

00000002

9846 C014

00000014

ALPHA1

4,6,20(12)

00000006

9846 C014

00000014

ALPHA2

R4,R6,20(BASE)

0000000A

9046 C020

00000020

BETA1

STM

4,6,AREA

0000000E

9046 C014

00000014

BETA2

STM

4,6,DISPL(BASE)

00000012

8920 000F

0000000F

GAMMA1

SLL

2,15

00000016

BF3E A400

00000400

DELTA1

ICM

3,B’1110’,1024(10)

0000001A

BF3D C02C

0000002C

DELTA2

ICM

R3,MASK,IMPLICIT

0000001E

07FE

R14 Return

0000000D

MASK

EQU

B’1101’

00000020

0000000000000000

AREA

3F’0’

00000014

DISPL

EQU

0000002C

C6D9C5C4

IMPLICIT DC

C’FRED’

END

When assembled, the object code for the instruction labeled ALPHA1

(statement 25),

in hexadecimal, is:

9846C014

where:

Is the operation code

Is register R₁

Is register R₃

Is base register B₁

014

Is displacement D₁ from base register B₁

When assembled, the object code for the instruction labeled DELTA1

(statement 30),

in hexadecimal, is:

BF3EA400

where:

Is the operation code

Is register R₁

Is mask M₃

Is base register B₁

400

Is displacement D₁ from base register B₁

RSI format

The operand fields of RSI-format instructions designate two registers and a 16 bit

immediate operand.

HLASM V1R6 Language Reference

Op Code

R₃

Symbols used to represent registers (see REG1 in the examples) are assumed to be

equated to absolute values 0 - 15.

The immediate value is treated as a signed binary integer representing the number

of halfwords to branch relative to the current location.

The branch target can be specified as a label in which case the assembler calculates

the immediate value and performs some checking of the value.

If the GOFF assembler option is active, you can specify the target address as an

external symbol or an expression that contains external symbols.

Example:

ALPHA9

BRXH

1,3,BETA9

where BETA9 is an external symbol.

The branch target can also be specified as an absolute value in which case the

assembler issues a warning before it assembles the instruction.

Examples:

ALPHA1

BRXH

REG1,REG3,BETA1

BETA1

BRXLE

1,2,ALPHA1

When assembled, the object code for the instruction labeled ALPHA1, in

hexadecimal, is

84130002

where:

Is the operation code

Is register REG1

Is register REG3

0002

Is the immediate data I2

RX format

The operand fields of RX-format instructions designate one or two registers,

including an index register, and a virtual storage address (coded as an implicit

address or an explicit address), with the following exception:

In BC branching instructions, a 4 bit branching mask (see 7 and TEN in the

instructions labeled LAMBDAn in the examples) with a value 0 - 15, replaces the

first register specification.

Op Code

X₂

Symbols used to represent registers (see REG1, INDEX, and BASE in the ALPHA2

instruction in the examples) are assumed to be equated to absolute values 0 - 15.

Chapter 4. Machine instruction statements

Symbols used to represent implicit addresses (see IMPLICIT in the instructions

labeled GAMMAn in the examples) can be either relocatable or absolute.

Symbols used to represent displacements (see DISPL in the instructions labeled

BETA2 and LAMBDA1 in the examples) in explicit addresses are assumed to be

equated to absolute values between 0 and 4095.

Examples:

ALPHA1

1,200(4,10)

ALPHA2

REG1,200(INDEX,BASE)

BETA1

2,200(,10)

BETA2

REG2,DISPL(,BASE)

GAMMA1

3,IMPLICIT

GAMMA2

3,IMPLICIT(INDEX)

DELTA1

4,=F’33’

LAMBDA1

7,DISPL(,BASE)

LAMBDA2

TEN,ADDRESS

When assembled, the object code for the instruction labeled ALPHA1, in

hexadecimal, is:

5814A0C8

where:

Is the operation code

Is register R₁

Is index register X₂

Is base register B₂

0C8

Is displacement D₂ from base register B₂

When assembled, the object code for the instruction labeled GAMMA1, in

hexadecimal, is:

5824xyyy

where:

Is the operation code

Is register R₁

Is the index register X₂

Is base register B₂

yyy

Is displacement D₂ from base register B₂

SI format

The operand fields of SI-format instructions designate immediate data and a

virtual storage address.

Op Code

Symbols used to represent immediate data (see HEX40 and TEN in the instructions

labeled ALPHA2 and BETA1 in the examples) are assumed to be equated to absolute

values 0 - 255.

Symbols used to represent implicit addresses (see IMPLICIT and KEY in the

instructions labeled BETA1 and BETA2) can be either relocatable or absolute.

HLASM V1R6 Language Reference

Symbols used to represent displacements (see DISPL40 in the instruction labeled

ALPHA2 in the examples) in explicit addresses are assumed to be equated to

absolute values 0 - 4095.

Examples:

ALPHA1

CLI

40(9),X’40’

ALPHA2

CLI

DISPL40(NINE),HEX40

BETA1

CLI

IMPLICIT,TEN

BETA2

CLI

KEY,C’E’

When assembled, the object code for the instruction labeled ALPHA1, in

hexadecimal, is:

95409028

where

Is the operation code.

Is the immediate data.

Is the base register.

028

Is the displacement from the base register

SS format

The operand fields and subfields of SS-format instructions designate two virtual

storage addresses (coded as implicit addresses or explicit addresses) and,

optionally, the explicit data lengths you want to include. However, in the Shift and

Round Decimal (SRP) instruction, a 4 bit immediate data field (see the operand 3

in the example of an SRP instruction), with a value 0 - 9, is specified as a third

operand.

Op Code

B₂

Op Code

L₁

L₂

B₂

Op Code

L₁

I₃

B₂

Op Code

R₁

R₃

B₂

Chapter 4. Machine instruction statements

Op Code

R₁

R₃

B₄

Symbols used to represent base registers (see BASE8 and BASE7 in the instruction

labeled ALPHA2 in the examples) in explicit addresses are assumed to be equated to

absolute values 0 - 15.

Symbols used to represent explicit lengths (see NINE and SIX in the instruction

labeled ALPHA2 in the examples) are assumed to be equated to absolute values 0 -

256 for SS-format instructions with one length specification, and 0 - 16 for

SS-format instructions with two length specifications.

Symbols used to represent implicit addresses (see FIELD1 and FIELD2 in the

instruction labeled ALPHA3, and FIELD1,X’8’ in the SRP instructions in the

examples) can be either relocatable or absolute.

Symbols used to represent displacements (see DISP40 and DISP30 in the instruction

labeled ALPHA5 in the examples) in explicit addresses are assumed to be equated to

absolute values 0 - 4095.

See page “Lengths” on page 87 for more information about the lengths of

SS-format instructions.

Examples:

ALPHA1

40(9,8),30(6,7)

ALPHA2

40(NINE,BASE8),30(SIX,BASE7)

ALPHA3

FIELD1,FIELD2

ALPHA4

AREA(9),AREA2(6)

ALPHA5

DISP40(,8),DISP30(,7)

BETA1

MVC

0(80,8),0(7)

BETA2

MVC

DISP0(,8),DISP0(7)

BETA3

MVC

TO,FROM

SRP

FIELD1,X’8’,3

When assembled, the object code for the instruction labeled ALPHA1, in

hexadecimal, is:

FA858028701E

where:

Is the operation code.

Is length L₁

Is length L₂

Is base register B₁

028

Is displacement D₁ from base register B₁

Is base register B₂

01E

Is displacement D₂ from base register B₂

When assembled, the object code for the instruction labeled BETA1, in hexadecimal,

is:

D24F80007000

where:

Is the operation code

Is length L

Is base register B₁

HLASM V1R6 Language Reference

000

Is displacement D₁ from base register B₁

Is base register B₂

000

Is displacement D₂ from base register B₂

Chapter 4. Machine instruction statements

HLASM V1R6 Language Reference

Chapter

5. Assembler instruction statements

This chapter describes, in detail, the syntax and usage rules of each assembler

instruction. There is also information about assembly instructions on “Conditional

assembly instructions” on page 257. The following table lists the assembler

instructions by type, and provides the number of the page where the instruction is

described.

Table 10. Assembler instructions

Type of Instruction

Instruction

Page No.

Program Control

AINSERT

“AINSERT

instruction” on

page 111

CNOP

“CNOP

instruction” on

page 122

COPY

“COPY

instruction” on

page 125

END

“END instruction”

on page 186

EXITCTL

“EXITCTL

instruction” on

page 192

ICTL

“ICTL instruction”

on page 194

ISEQ

“ISEQ instruction”

on page 195

LTORG

“LTORG

instruction” on

page 198

ORG

“ORG instruction”

on page 205

POP

“POP instruction”

on page 208

PUNCH

“PUNCH

instruction” on

page 213

PUSH

“PUSH

instruction” on

page 214

REPRO

“REPRO

instruction” on

page 215

Table 10. Assembler instructions (continued)

Type of Instruction

Instruction

Page No.

Listing Control

CEJECT

“CEJECT

instruction” on

page 121

EJECT

“EJECT

instruction” on

page 186

“PRINT

instruction” on

page 209

SPACE

“SPACE

instruction” on

page 217

TITLE

“TITLE

instruction” on

page 219

Operation Code Definition

OPSYN

“OPSYN

instruction” on

page 202

100

HLASM V1R6 Language Reference

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