High Level Assembler for z/OS & z/VM & z/VSE. Language Reference (Version 1 Release 6) - page 5
this class are empty. (“PRV” is the binder's term for a “Pseudo Register Vector”,
the cumulative collection of external dummy sections.)
v High Level Assembler assigns the name of the section as an entry name at the
initial byte of B_TEXT, and assigns to it the AMODE of the section name.
These two classes are bound in the same way as ordinary control sections. Dummy
external sections are bound in the load module model. They can be used to
generate a load module if certain restrictions are satisfied.
You can declare other classes in addition to the defaults, but the resulting program
object is not convertible to a load module.
Parts (z/OS and CMS)
Parts are the smallest externally named and independently relocatable subdivisions
of elements in a merge class. A class containing parts can contain only parts, and a
class containing anything other than parts cannot contain any parts.
ENTRY statements cannot define an entry point in a part.
You define a part with the CATTR instruction, which must follow the initiation of
an executable section. The name of the class to which the part belongs is provided
in the name entry of the CATTR instruction, and the name of the part is specified
as an operand. The first definition of a class name can also specify the attributes of
the class. (See “CATTR instruction (z/OS and CMS)” on page 115 for further
information.)
For example, suppose you define two parts in a class:
SECT_B CSECT ,
Define section SECT_B
PClass CATTR Part(Part_R),RMODE(ANY) Define class PClass, part Part_R
- - -
Statements included in Part_R
PClass CATTR Part(Part_S) Define part Part_S in class PClass
- - -
Statements included in Part_S
PClass CATTR Part(Part_R) Resume class PClass and part Part_R
- - -
More statements included in Part_R
These statements define a “merge” class PClass containing two parts, Part_R and
Part_S. If other classes or other object files declare parts with the same names in
the same class, the binder merges their contents to determine the final part
definition in the program object.
You can provide additional statements for a part by specifying a CATTR statement
with the class name in the name entry and the part name specified as the operand.
No other class attributes can be specified following the first CATTR statement
declaring the class.
Parts are automatically assigned a “merge” attribute, meaning that more than one
identically named part might appear in a class defined in other assemblies or
compilations. The binder assigns the longest length and strictest alignment of all
such identically named parts, and merges the machine language text contributions
of each to form the final text belonging to that part. The order of text merging
depends on the sequence of parts processing by the binder.
Note: During linking, parts might be arranged in any order, depending on their
priority attribute. Do not assume any ordering relationship among parts.
Chapter 3. Program structures and addressing
61
Location counter setting
The assembler maintains a separate location counter for each section, element, and
part. The location counter setting for the first section starts at 0, except when an
initial section is started with a START instruction that specifies a nonzero location
counter value. The location values assigned to the instructions and other data in a
section, element, or part are, therefore, relative to the location counter setting at the
beginning of that section, element, or part.
For executable sections, the location values that appear in the listings depend on
the THREAD option:
v If you specify NOTHREAD, the location counter values for each section,
element, or part restart at 0, except possibly those associated with a first section
initiated by a START instruction with a nonzero address.
v If you specify THREAD, location counter values do not restart at 0 for each
subsequent section, element, or part. They continue, after suitable alignment,
from the end of the previous section, element, or part.
For reference control sections, the location values that appear in the listings always
start from 0.
You can continue a control section, element, or part that has been discontinued and
thus intersperse code sequences from different control sections, elements, or parts.
The location values that appear in the listings for such discontiguous sequences are
divided into segments that follow from the end of one segment to the beginning of
the subsequent segment.
The location values, listed for the next defined control section, element, or part,
begin after the last location value assigned to the preceding such item.
On z/VSE, or when you specify the NOGOFF assembler option on z/OS and
CMS, the maximum value of the location counter and the maximum length of a
control section is 224-1, or X'FFFFFF' bytes. If LIST(133) is in force, then the
high-order byte is shown as zero.
z/VM and z/OS
When you specify the GOFF assembler option, the maximum value of the
location counter and the maximum length of an element or part is 231-1, or
X'7FFFFFFF' bytes.
Location counter and length limits
The assembler also maintains a length counter for each individually relocatable
component of the program: executable and reference control sections, elements,
and parts.
If any location counter overflows its maximum value, High Level Assembler issues
the severe error message:
ASMA039S Location counter error
and continues assembling with the location counter value “wrapping” around to
zero.
The length of a section, element, or part cannot exceed the maximum allowed
length described above. If the length counter reaches this maximum value, it stays
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HLASM V1R6 Language Reference
fixed at that value without an error condition or error message. Exceeding the
length counter causes overflow of the location counter, producing the ASMA039S
message.
The location counter setting is relative to the beginning of the location it
represents, and the length counter represents the cumulative length of the control
section. This means that the length counter is nearly always greater than the
location counter, and can exceed its maximum value before the location counter.
Even if the location counter overflows, the length counter value might be correct,
and reassembling with the NOTHREAD option might avoid the location counter
overflow condition.
Use of multiple location counters
High Level Assembler lets you use multiple location counters for each individual
control section. Use the LOCTR instruction (see “LOCTR instruction” on page 196)
to assign different location counters to different parts of a control section. The
assembler then rearranges and assembles the coding together, according to the
different location counters you have specified:
v All coding using the first location counter is assembled together.
v Then the coding using the second location counter is assembled together.
v And so on, for futher location counters.
An example of the use of multiple location counters is shown in Figure 15. In the
example, executable instructions and data areas have been interspersed throughout
the coding in their logical sequence. Each group of instructions is preceded by a
LOCTR instruction that identifies the location counter under which it is to be
assembled. The assembler rearranges the control section so that the executable
instructions are grouped together and the data areas are grouped together. Symbols
are not resolved in the order they appear in the source program, but in location
counter sequence.
SOURCE MODULE
LINKED MODULE
(shown in source code format)
┌──────────────────────────────────┐
┌──────────────────────────────────┐
─┐
│ INST
CSECT
│
│
│ controlled
│
│
LR
12,15
├──────────────────►│
LR
12,15
│ by INST
│
│
USING INST,12
├──────────────────►│
USING INST,12
│ location
│
│
│
│
│ counter
│
│
│┌─────────────────►│
TM
CODE,X’03’
│
│
│ DATA
LOCTR
││┌────────────────►│
BM
NEWREC
│
│
│ INPUTREC DS
0CL80
├┼┼───────────┐
│
│
│
│ RECCODE DS
CL1
├┼┼─────────┐ │
│
│
│ control
│
│││
│ │
│
│
├── section
│ INST
LOCTR
│││
│ │
│
│
│ INST
│
TM
CODE,X’03’
├┘│
│ │
├ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ── ─ ┤
│
│
BM
NEWREC
├─┘
│ !────►│ INPUTREC DS
0CL80
│ controlled
│
│
│
!──────►│ RECCODE DS
CL1
│ by DATA
│
│ DATA
LOCTR
│
│
│ location
│
│ VAL1
DC
F’56’
├──────────────────►│ VAL1
DC
F’56’
│ counter
│
│ VAL2
DC
F’84’
├──────────────────►│ VAL2
DC
F’84’
│
│
│
│
│
│
│
│
│
├──────────────────────────────────┤
─┘
│ NEXT
CSECT
│
│
│ control
│
│
│
│ section
│
│
│
│ NEXT
Figure 15. Use of multiple location counters
The interactions of the LOCTR instruction with sections, classes, and parts is
described at “LOCTR instruction” on page 196.
Chapter 3. Program structures and addressing
63
Addressing
This part of the chapter describes the techniques and introduces the instructions
that let you use symbolic addresses when referring to instructions and data. You
can address code and data that is defined within the same source module, or code
and data that is defined in another source module. Symbolic addresses are more
meaningful and easier to use than the corresponding object code addresses
required for machine instructions. The assembler can convert the symbolic
addresses you specify into their object code form.
The z/Architecture architecture has two ways of resolving addresses in your
program, depending on the machine instruction type:
v base displacement, where the address is computed by adding the displacement
to the contents of a base register.
v relative immediate, where the address is computed by adding 2 × the signed
immediate operand field to the instruction's address (refer to “RI format” on
page 88 and “RSI format” on page 92).
Addressing within source modules: establishing
addressability
You can use symbolic addresses in machine instructions and certain assembler
instructions. This is much easier than explicitly coding the addresses in the form
required by the hardware. Symbolic addresses you code in the instruction
operands are implicit addresses, and addresses in which you specify the
base-displacement or intermediate form are explicit addresses.
The assembler converts your implicit addresses into the explicit addresses required
for the assembled object code of the machine instruction. However, for
base-displacement operands, you must first establish addressability, as described
below.
Base Address Definition: A base address is the storage address that a given location
counter value refers to when the program is loaded into memory. The location
counter value is the location within the program (it is fixed relative to the start of
the program). The corresponding storage address depends on where in memory
the program is loaded.
How to establish addressability
To establish the addressability of a control section, element, or part (see “Sections,
elements, and parts” on page 53), you must:
v Specify a base address from which the assembler can compute displacements to
the addresses within the control section, element, or part.
v Assign the base registers to contain the base addresses.
v Write the instructions that load the base registers with the base addresses.
The following example shows the base address at MYPROG, that is assigned by
register 12. Register 12 is loaded with the value in register 15. By convention,
register 15 contains the storage address (set by the operating system) of the control
section (CSECT) when the program is loaded into storage at execution time.
MYPROG CSECT
The base address
USING MYPROG,12
Assign the base register
LR
12,15
Load the base address
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HLASM V1R6 Language Reference
Similarly, you can use a BASR or similar instruction to put the address of the
following instruction into register 12.
BASR
12,0
USING *,12
The USING instruction indicates that register 12 can be used as a base register
containing that address.
During assembly, the implicit addresses you code are converted into their explicit
base-displacement form; then, they are assembled into the object code of the
machine instructions in which they have been coded.
During execution, the base address is loaded into the base register.
z/VM and z/OS
If you specify multiple classes, you must provide addressability for each
element. For example, suppose you define two classes that must reference
positions in the other:
MYPROG CSECT ,
CLASS_A CATTR RMODE(24)
Define class CLASS_A
BASR
12,0
Local base register
USING *,12
Addressability for this element
- - -
L
1,Addr_B
Address of BDATA in CLASS_B
USING BDATA,1
- - -
ADATA
DS
F
Data in CLASS_A
Addr_B
DC
A(BDATA)
- - -
CLASS_B CATTR RMODE(31)
Define class CLASS_B
BASR
11,0
Local base register
USING *,11
Addressability for this element
- - -
L
2,Addr_A
Address of ADATA in CLASS_A
USING ADATA,2
- - -
BDATA
DS
D
Data in CLASS_B
Addr_A
DC
A(ADATA)
A class specifying the “deferred load” (DEFLOAD) attribute on its defining
CATTR statement cannot be referenced from other classes using A-type or
V-type address constants. However, A-type and V-type address constants
can be used within a deferred-load class to refer to locations within that
class or within any default_load (LOAD) class.
The loading service for deferred-load classes provides the origin address of
the deferred-load segment containing the classes. You can then use Q-type
address constants in other classes to calculate the addresses of items in the
loaded classes. For example:
MYPROG CSECT ,
CLASS_A CATTR RMODE(31)
BASR
12,0
Set base register
USING *,12
Addressability for this element
- - -
* Address of CLASS_B segment assumed to be returned in register 8
- - -
A
8,BDATAOff
Add offset of BDATA in CLASS_B
USING BDATA,8
- - -
BDATAOff DC
Q(BDATA)
Offset of BDATA
- - -
Chapter 3. Program structures and addressing
65
CLASS_B CATTR DEFLOAD,RMODE(ANY) Define deferred-load class
- - -
BDATA
DS
F
Data in deferred-load class
Parts must always be referenced from LOAD classes using Q-type address
constants using the techniques shown in this example, whether or not they
reside in deferred load classes. This is because parts are subject to
reordering during binding. As noted above, parts can reference other parts
in the same class using A-type and V-type address constants.
Base register instructions
The USING and DROP assembler instructions enable you to use expressions
representing implicit addresses as operands of machine instruction statements,
leaving the assignment of base registers and the calculation of displacements to the
assembler.
In order to use symbols in implicit addresses in the operand field of machine
instruction statements, you must:
v Code a USING instruction to assign one or more base registers to a base address
or sequence of base addresses
v Code machine instructions to load each base register with the base address
Having the assembler determine base registers and displacements relieves you of
the need to separate each address into an explicit displacement value and an
explicit base register value. This feature of the assembler eliminates a likely source
of programming errors, thus reducing the time required to write and test
programs. You use the USING and DROP instructions to take advantage of this
feature. For information about how to use these instructions, see “USING
instruction” on page 222 and “DROP instruction” on page 176.
Qualified addressing
Qualified addressing lets you use the same symbol to refer to data in different
storage locations. Qualified symbols are ordinary symbols prefixed by a symbol
qualifier and a period. A symbol qualifier is used to specify which base register the
assembler should use when converting an implicit address into its explicit
base-displacement form. Before you use a symbol qualifier, you must have
previously defined it in the name entry of a labeled USING instruction. For
information about labeled USING instructions, see “USING instruction” on page
222. When defined, you can use a symbol qualifier to qualify any symbol that
names a storage location within the range of the labeled USING. Qualified symbols
can be used anywhere a relocatable term can be used.
The following examples show the use of qualified symbols. SOURCE and TARGET are
both symbol qualifiers previously defined in two labeled USING instructions. X
and Y are both symbols that name storage locations within the range of both
labeled USING instructions.
MVC
TARGET.X,SOURCE.X
MVC
TARGET.Y+5(3),SOURCE.Y+5
XC
TARGET.X+10(L’X-10),TARGET.X+10
LA
2,SOURCE.Y
Dependent addressing
Dependent addressing lets you minimize the number of base registers required to
refer to data by making greater use of established addressability. For example, you
might want to describe the format of a table of data defined in your source module
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HLASM V1R6 Language Reference
with a dummy control section (see “Dummy control sections” on page 57). To refer
to the data in the table using the symbols defined in the dummy section, you need
to establish the addressability of the dummy section. To do this you must:
v Code a USING instruction to assign one or more base registers to a base
address.
v Code machine instructions to load each base register with the base address.
However, dependent addressing offers an alternative means of establishing
addressability of the dummy section.
Establish addressability of the control section in which the table is defined. Then
you can establish addressability of the dummy section by coding a USING
statement which specifies the name of the dummy section and the address of the
table. When you refer to the symbols in the dummy section, the assembler uses the
already established addressability of the control section when converting the
symbolic addresses into their base-displacement form.
For example, suppose addressability has been established for a control section
containing a data structure that is mapped by a dummy control section:
DATAMAP DSECT ,
DSECT describing data structure
FIELD1
DS
F
FIELD2
DS
CL32
FIELD3
DS
CL24
- - -
CODE
CSECT ,
Program code
BASR
12,0
Set base register
USING *,12
Provide addressability
- - -
USING DATAMAP,REALDATA Map DSECT onto REALDATA
L
2,FIELD1
Register 12 is base register
LA
3,FIELD3
Address of DATA3
- - -
REALDATA DS
0F
Data mapped by DATAMAP
DATA1
DC
F’32’
DATA2
DC
CL32’Actual Data’
DATA3
DC
CL24’Additional Data’
Relative addressing
Relative addressing is the technique of addressing instructions and data areas by
designating their location in relation to the location counter or to some symbolic
location. This type of addressing is always in bytes—never in bits, words, or
instructions. Thus, the expression *+4 specifies an address that is 4 bytes greater
than the current value of the location counter. In the sequence of instructions in the
following example, the location of the CR machine instruction can be expressed in
two ways, ALPHA+2, or BETA-4, because all the machine instructions in the example
are 2-byte instructions.
ALPHA
LR
3,4
CR
4,6
BCR
1,14
BETA
AR
2,3
Literal pools
Literals, collected into pools by the assembler, are assembled as part of the
executable control section to which the pools belong. The pools are built when an
LTORG instruction is processed. If no LTORG instruction is specified, a literal pool
containing all the literals used in the whole source module is assembled at one of:
v The end of the first control section.
v The end of the B_TEXT class belonging to the first section.
Chapter 3. Program structures and addressing
67
This literal pool appears in the listings after the END instruction. For more
information about the LTORG instruction, see “LTORG instruction” on page 198.
Independently Addressed Segments: If any control section is divided into
independently addressed segments, an LTORG instruction should be specified at
the end of each segment to create a separate literal pool for that segment.
Establishing residence and addressing mode
The AMODE and RMODE instructions specify the addressing mode (AMODE) and
the residence mode (RMODE) to be associated with control sections in the object
deck. You can specify AMODE for ENTRY, EXTRN, and WXTRN instruction
operands if the GOFF option is specified. If OBJ format is used, then AMODE is
not valid for ENTRY, EXTRN, or WXTRN instruction operands. AMODE and
RMODE can be specified for any CSECT or START operand with either OBJ or
GOFF and without restriction on the xMODE operands. These modes can be
specified for these types of control sections:
v Control section (for example START, CSECT)
v Unnamed control section
v Common control section (COM instruction)
The assembler sets the AMODE and RMODE indicators in the ESD record for each
applicable external symbol in an assembly. The linker stores the AMODE and
RMODE values in the bound program. They are later used by the loader program
that brings the load module into storage. The loader program uses the RMODE
value to determine where it loads the load module, and passes the AMODE value
of the executable program's main entry point to the operating system to establish
the addressing mode.
z/VM and z/OS
When you specify the GOFF option:
v The RMODE value specified for a section is by default assigned to the
B_TEXT class.
v The AMODE specified for the section is assigned to an entry point
having the section name and the location of the first byte of class B_TEXT.
If the source program defines additional classes, each class might be
assigned its own RMODE, and an entry point in any class might be
assigned its own AMODE.
For more information about the AMODE and RMODE instructions, see “AMODE
instruction” on page 113 and “RMODE instruction” on page 215.
Symbolic linkages
Symbols can be defined in one module and referred to in another, which results in
symbolic linkages between independently assembled program sections. These
linkages can be made only if the assembler can provide information about the
linkage symbols to the linker, which resolves the linkage references at link-edit
time.
Establishing symbolic linkage
You must establish symbolic linkage between source modules so that instructions
in one source module can refer to or branch to symbolic locations defined in other
(external) source modules. You do this by using external symbol definitions and
external symbol references. To establish symbolic linkage with an external source
module, you must do the following:
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HLASM V1R6 Language Reference
v In the current source module, you must identify the symbols that are not
defined in that source module, if you want to use them in instruction operands.
These symbols are called external symbols, because they are defined in another
(external) source module. You identify external symbols in the EXTRN or
WXTRN instruction, or the V-type address constant. For more information about
the EXTRN and WXTRN instructions, see “EXTRN instruction” on page 193 and
“WXTRN instruction” on page 232.
v In the external source modules, you must identify the symbols that are defined
in those source modules, and that you refer to from the current source module.
The two types of definitions that you can use are control section names (defined
by the CSECT, RSECT, and START instructions), and entry symbols. Entry
symbols are so called because they provide points of entry to a control section in
a source module. You identify entry symbols with the ENTRY instruction. For
more information about the ENTRY instruction, see “ENTRY instruction” on
page 187.
v Reference external symbols using one of these methods:
- Provide the A-type or V-type address constants needed by the assembler to
reserve storage for the addresses represented by the external symbols.
- Reference an external symbol in the same class in a relative branch
instruction.
The assembler places information about entry and external symbols in the external
symbol dictionary. The linker uses this information to resolve the linkage addresses
identified by the entry and external symbols.
Referring to external data
Use the EXTRN instruction to identify the external symbol that represents data in
an external source module, if you want to refer to this data symbolically.
For example, you can identify the address of a data area as an external symbol and
load the A-type address constant specifying this symbol into a base register. Then,
you use this base register when establishing the addressability of a dummy section
that describes this external data. You can now refer symbolically to the data that
the external area contains.
You must also identify, in the source module that contains the data area, the
address of the data as an entry symbol.
Branching to an external address
Use the V-type address constant to identify the external symbol that represents the
address in an external source module that you want to branch to.
For example, you can load into a register the V-type address constant that
identifies the external symbol. Using this register, you can then branch to the
external address represented by the symbol.
If the symbol is the name entry of a START, CSECT, or RSECT instruction in the
other source module, and thus names an executable control section, it is
automatically identified as an entry symbol. If the symbol represents an address in
the middle of a control section, you must identify it as an entry symbol for the
external source module.
You can also use a combination of an EXTRN instruction to identify, and an A-type
address constant to contain, the external branch address. However, the V-type
address constant is more convenient because:
Chapter 3. Program structures and addressing
69
v You do not have to use an EXTRN instruction.
v The external symbol you specify, can be used in the name entry of any other
statement in the same source program.
v It works correctly even if the program is linked as an overlay module, so long as
the reference is not to a symbol in an exclusive segment. See z/OS MVS Program
Management: User's Guide and Reference, SA22-7643 for further information.
The following example shows how you use an A-type address constant to contain
the address of an external symbol that you identify in an EXTRN instruction. You
cannot use the external symbol name EXMOD1 in the name entry of any other
statement in the source program.
L
15,EX_SYM
Load address of external symbol
BASR
14,15
Branch to it
EX_SYM DC
A(EXMOD1)
Address of external symbol
EXTRN EXMOD1
Identify EXMOD1 as external symbol
The following example shows how you use the symbol EXMOD1 as both the name of
an external symbol and a name entry on another statement.
L
15,EX_SYM
Load address of external symbol
BASR
14,15
Branch to it
EXMOD1
DS
0H
Using EXMOD1 as a name entry
EX_SYM DC
V(EXMOD1)
Address of external symbol
If the external symbol that represents the address to which you want to branch is
part of an overlay-structured module, identify it with a V-type address constant.
Do not use an EXTRN instruction and an A-type address constant. You can use the
supervisor CALL macro instruction to branch to the address represented by the
external symbol. The CALL macro instruction generates the necessary V-type
address constant.
z/VM and z/OS
You can branch to external symbols in the same class using relative branch
instructions.
MYPROG CSECT ,
Define section MYPROG
CLASS_A CATTR RMODE(31)
Define class CLASS_A
- - -
BRAS
14,ENTRYB
Branch to external symbol
- - -
HISPROG CSECT ,
Define section HISPROG
CLASS_A CATTR RMODE(31)
Define class CLASS_A
- - -
ENTRYB STM
14,12,12(13) Entry point referenced externally
- - -
END
You can also use a relative branch instruction to branch to an externally
defined symbol:
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HLASM V1R6 Language Reference
MYPROG CSECT ,
Define section MYPROG
MYCLASS CATTR RMODE(31)
Define class MYCLASS
EXTRN TARGET
Declare external symbol TARGET
- - -
BRAS
14,TARGET
Branch to external symbol
- - -
END
A separate source module must define the entry point TARGET in class
MYCLASS.
Establishing an external symbol alias
You can instruct the assembler to use an alias for an external symbol in place of
the external symbol itself, when it generates the object module. To do this you
must code an ALIAS instruction which specifies the external symbol and the alias
you want the assembler to use. The external symbol must be defined in a START,
CSECT, RSECT, ENTRY, COM, DXD, external DSECT, EXTRN, or WXTRN
instruction, or in a V-type address constant.
The following example shows how you use the ALIAS instruction to specify an
alias for the external symbol EXMOD1.
L
15,EX_SYM
Load address of external symbol
BASR
14,15
Branch to it
EXMOD1
DS
0H
Using EXMOD1 as a name entry
EX_SYM DC
V(EXMOD1)
Address of external symbol
EXMOD1
ALIAS C’XMD1PGM’
XMD1PGM is the real external name
See “ALIAS instruction” on page 112 for information about the ALIAS instruction.
External symbol dictionary entries
For each section, class, part, entry, external symbol, and dummy external control
section, the assembler keeps a record of the following external symbol dictionary
(ESD) information: List level 1 start
v Symbolic name, if one is specified
v Type code
v Individual identification number (ESDID)
v Starting address
v Length
v Owning ESDID, if any
v Symbol attributes
v Alias, if one is specified
Refer to “External Symbol Dictionary (ESD)” in the HLASM Programmer's Guide
Table 7 on page 72 lists the assembler instructions that define control sections and
dummy control sections, classes and parts, or identify entry and external symbols,
and tells their associated type codes. You can define up to 65535 individual control
sections and external symbols in a source module if the NOGOFF option is
specified, or up to 999999 external symbols if the GOFF option is specified.
Chapter 3. Program structures and addressing
71
Table 7. Defining external symbols
Coding Entered into External
Name Entry
Instruction
Symbol Dictionary
NOGOFF option GOFF option
If present
START, CSECT, or RSECT
SD
SD, ED, LD
If omitted
START, CSECT, or RSECT
PC
SD,ED
Instruction-
Any instruction that initiates
PC
SD
dependent
the unnamed section
If present
COM
CM
SD,ED,CM
If omitted
COM
CM
SD,ED
Optional
DSECT
None
None
Mandatory
DXD or external DSECT
XD
XD
Mandatory
CATTR
Not applicable
ED
Mandatory
CATTR PART(name)
Not applicable
PD
Not applicable
ENTRY
LD
LD
Not applicable
EXTRN
ER
ER
Not applicable
DC (V-type address constant)
ER
ER
Not applicable
WXTRN
WX
WX
See the appendix “Object Deck Output” in the HLASM Programmer's Guide for
details about the ESD entries produced when you specify the NOGOFF assembler
option.
z/VM and z/OS
Refer to z/OS MVS Program Management: Advanced Facilities, SA22-7644 for
details about the ESD entries produced when you specify the GOFF
assembler option.
Summary of source and object program structures
The differences between the load module model and the program object model,
and their interactions with assembler language instructions, are summarized in the
following table:
Table 8. Object program structure comparison
Property
“Load Module” Model
“Program Object” Model
Form of object program
One-dimensional module
Two-dimensional module
Smallest indivisible independently
Control section
Element and part
relocatable component
Residence Mode
Only one
One per class
Addressing Mode
Only one
One per entry point
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HLASM V1R6 Language Reference
Table 8. Object program structure comparison (continued)
Property
“Load Module” Model
“Program Object” Model
Compatibility
Can be converted to program object
Can be converted to load module
with limitations
Assembler Option
NOGOFF or GOFF
GOFF only
Assembler statements
CSECT, RSECT, START
CSECT, RSECT, START, CATTR,
XATTR
Assignable loadable-program
RMODE
RMODE, alignment, load type
attributes
External symbol types
SD/CM, LD, ER/WX, PR
SD, ED, LD, ER/WX, PR, PD
External symbol maximum length
8 characters
256 characters
External symbol scope
Module (WX), Library (ER)
Section, Module, Library,
Import/Export
External symbol attributes
AMode, RMode
AMode, RMode, scope, PSect name,
linkage type, reference type, extended
attributes
Object module record types
ESD, TXT, RLD, END, SYM
HDR, ESD, TXT, RLD, END, LEN
Address constant types
A, V, Q, CXD
A, V, Q, J, R, CXD
Binding attributes
Catenate (SD),Merge-like (CM,PR)
Catenate (non-Merge classes), Merge
classes (Parts, Pseudo-Registers)
Text types
Byte stream
Byte stream, records (structured and
unstructured)
Maximum contiguous text length
16 MB
1 GB
Chapter 3. Program structures and addressing
73
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HLASM V1R6 Language Reference
Chapter
4. Machine instruction statements
This chapter introduces a sample of the more common instruction formats and
provides general rules for coding them in their symbolic assembler language
format.
For the complete specifications of machine instructions, their object code format,
their coding specifications, and their use of registers and virtual storage areas, see
the applicable z/Architecture Principles of Operation manual for your processor.
At assembly time, the assembler converts the symbolic assembler language
representation of the machine instructions to the corresponding object code. The
computer processes this object code at execution time. Thus, the functions
described in this section can be called execution-time functions.
Also at assembly time, the assembler creates the object code of the data constants
and reserves storage for the areas you specify in your data definition assembler
instructions, such as DC and DS (see Chapter 5, “Assembler instruction
statements,” on page 99). At execution time, the machine instructions can refer to
these constants and areas, but the constants themselves are not normally processed.
As defined in the z/Architecture Principles of Operation information. there are five
categories of machine instructions:
v General instructions
v Decimal instructions
v Floating-Point instructions
v Control instructions
v Input/Output operations
Each is discussed in the following sections.
General instructions
Use general instructions to manipulate data that resides in general registers or in
storage, or that is introduced from the instruction stream. General instructions
include fixed-point, logical, and branching instructions. In addition, they include
unprivileged status-switching instructions. Some general instructions operate on
data that resides in the PSW or the TOD clock.
The general instructions treat data as four types: signed binary integers, unsigned
binary integers, unstructured logical data, and decimal data. Data is treated as
decimal by the conversion, packing, and unpacking instructions.
For further information, see “General Instructions” in the z/Architecture Principles of
Operation information.
Decimal instructions
Use the decimal instructions when you want to do arithmetic and editing
operations on data that has the binary equivalent of decimal representation.
Decimal data is represented in either zoned or packed format. In the zoned format,
the rightmost four bits of a byte are called the numeric bits and normally consist of
75
a code representing a decimal digit. The leftmost four bits of a byte are called the
zone bits, except for the rightmost byte of a decimal operand; these bits are treated
as a zone or a sign.
In the packed format, each byte contains two decimal digits, except for the rightmost
byte, which contains a sign to the right of a decimal digit.
Decimal instructions treat all numbers as integers. For example, 3.14, 31.4, and 314
are all processed as 314. You must keep track of the decimal point yourself. The
integer and scale attributes discussed in “Data attributes” on page 325 can help
you do this.
Additional operations on decimal data are provided by several of the instructions
in “General Instructions” in the z/Architecture Principles of Operation information.
Decimal operands always reside in storage.
For further information, see “Decimal Instructions” in the applicable z/Architecture
Principles of Operation manual.
Floating-point instructions
Use floating-point instructions when you want to do arithmetic operations on data
in any of the floating point formats. Thus, you do not have to keep track of the
decimal point in your computations. Floating-point instructions also let you do
arithmetic operations on both large numbers and small numbers, normally
providing greater precision than fixed-point decimal instructions.
For further information, see “Floating-Point Instructions” in the z/Architecture
Principles of Operation information.
Control instructions
Control instructions include all privileged and semiprivileged machine instructions,
except the input/output instructions described in “Input/output operations.”
Privileged instructions are processed only when the processor is in the supervisor
state. An attempt to process an installed privileged instruction in the problem state
generates a privileged-operation exception.
Semiprivileged instructions are those instructions that can be processed in the
problem state when certain authority requirements are met. An attempt to process
an installed semiprivileged instruction in the problem state when the authority
requirements are not met generates a privileged-operation exception or some other
program-interruption condition depending on the particular requirement that is
violated.
For further details, see “Control Instructions” in the z/Architecture Principles of
Operation information.
Input/output operations
Use the input/output instructions (instead of the IBM-supplied system macro
instructions) when you want to control your input and output operations more
closely.
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HLASM V1R6 Language Reference
The input or output instructions let you identify the channel or the device on
which the input or output operation is to be done. For information about how and
when you can use these instructions, see the applicable system manual.
For more information, see “Input/Output Operations” in the applicable
z/Architecture Principles of Operation manual and the applicable system manuals.
Branching with extended mnemonic codes
Branch instructions let you specify an extended mnemonic code for the condition on
which a branch is to occur. Thus, you avoid having to specify the mask value, that
represents the condition code, required by the BC, BCR, and BRC machine
instructions. The assembler translates the extended mnemonic code into the mask
value, and then assembles it into the object code of the BC, BCR, or BRC machine
instruction.
The extended branch mnemonics for the BC instruction require a base register; the
extended mnemonics for the BCR and BRC instructions do not. The extended
mnemonics for the BRC instruction begin with the letter “J”, and are sometimes
called “Jump” instructions, as indicated in Figure 16 on page 78.
Some typical extended mnemonic codes are given in Figure 16 on page 78. They
can be used as operation codes for branching instructions, replacing the BC, BCR,
and BRC machine instruction codes (see ▌1▐ in Figure 16 on page 78). The first
operand (see ▌2▐ in Figure 16 on page 78) of the BC, BCR, and BRC instructions
must not be present in the operand field (see ▌3▐ in Figure 16 on page 78) of the
extended mnemonic branching instructions.
For the complete list of branch mnemonics, see the latest edition of z/Architecture
Reference Summary (SA22-7871).
Chapter 4. Machine instruction statements
77
Extended Code
Meaning
Format
(Symbolic) Machine
Instruction Equivalent
──────────────────────────────────────────────────────────────────────────────────────────────────────
▌3▐
▌4▐
▌1▐
│
⌂
│
┌────▌2▐
│
┌───────┐
⌂
⌂
B
!─►D₂(X₂,B₂)
┐
Unconditional Branch
RX
BC
15,D₂(X₂,B₂)
BR
R₂
┘
RR
BCR
15,R₂
J
label
Unconditional Jump
RI
BRC
15,label
NOP
D₂(X₂,B₂)
┐
No Operation
RX
BC
0,D₂(X₂,B₂)
NOPR
R₂
│
RR
BCR
0,R₂
JNOP
label
┘
RI
BRC
0,label
Used After Compare
Instructions
BH
D₂(X₂,B₂)
┐
Branch on High
RX
BC
2,D₂(X₂,B₂)
BHR
R₂
┘
RR
BCR
2,R₂
JH
label
Jump on High
RI
BRC
2,label
BL
D₂(X₂,B₂)
┐
Branch on Low
RX
BC
4,D₂(X₂,B₂)
BLR
R₂
┘
RR
BCR
4,R₂
JL
label
Jump on Low
RI
BRC
4,label
BE
D₂(X₂,B₂)
┐
Branch on Equal
RX
BC
8,D₂(X₂,B₂)
BER
R₂
┘
RR
BCR
8,R₂
JE
label
Jump on Equal
RI
BRC
8,label
BNH
D₂(X₂,B₂)
┐
Branch on Not High
RX
BC
13,D₂(X₂,B₂)
BNHR
R₂
┘
RR
BCR
13,R₂
JNH
label
Jump on Not High
RI
BRC
13,label
BNL
D₂(X₂,B₂)
┐
Branch on Not Low
RX
BC
11,D₂(X₂,B₂)
BNLR
R₂
┘
RR
BCR
11,R₂
JNL
label
Jump on Not Low
RI
BRC
11,label
BNE
D₂(X₂,B₂)
┐
Branch on Not Equal
RX
BC
7,D₂(X₂,B₂)
BNER
R₂
┘
RR
BCR
7,R₂
JNE
label
Jump on Not Equal
RI
BRC
7,label
Figure 16. Extended mnemonic codes (part 1 of 5)
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HLASM V1R6 Language Reference
Used After Arithmetic Instructions
BP
D₂(X₂,B₂)
┐
Branch on Plus
RX
BC
2,D₂(X₂,B₂)
BPR
R₂
┘
RR
BCR
2,R₂
JP
label
Jump on Plus
RI
BRC
2,label
BM
D₂(X₂,B₂)
┐
Branch on Minus
RX
BC
4,D₂(X₂,B₂)
BMR
R₂
┘
RR
BCR
4,R₂
JM
label
Jump on Minus
RI
BRC
4,label
BZ
D₂(X₂,B₂)
┐
Branch on Zero
RX
BC
8,D₂(X₂,B₂)
BZR
R₂
┘
RR
BCR
8,R₂
JZ
label
Jump on Zero
RI
BRC
8,label
BO
D₂(X₂,B₂)
┐
Branch on Overflow
RX
BC
1,D₂(X₂,B₂)
BOR
R₂
┘
RR
BCR
1,R₂
JO
label
Jump on Overflow
RI
BRC
1,label
BNP
D₂(X₂,B₂)
┐
Branch on Not Plus
RX
BC
13,D₂(X₂,B₂)
BNPR
R₂
┘
RR
BCR
13,R₂
JNP
label
Jump on Not Plus
RI
BRC
13,label
BNM
D₂(X₂,B₂)
┐
Branch on Not Minus
RX
BC
11,D₂(X₂,B₂)
BNMR
R₂
┘
RR
BCR
11,R₂
JNM
label
Jump on Not Minus
RI
BRC
11,label
BNZ
D₂(X₂,B₂)
┐
Branch on Not Zero
RX
BC
7,D₂(X₂,B₂)
BNZR
R₂
┘
RR
BCR
7,R₂
JNZ
label
Jump on Not Minus
RI
BRC
7,label
BNO
D₂(X₂,B₂)
┐
Branch on No Overflow
RX
BC
14,D₂(X₂,B₂)
BNOR
R₂
┘
RR
BCR
14,R₂
JNO
label
Jump on No Overflow
RI
BRC
14,label
Figure 17. Extended mnemonic codes (part 2 of 5)
Used After Test Under Mask Instructions
BO
D₂(X₂,B₂)
┐
Branch if Ones
RX
BC
1,D₂(X₂,B₂)
BOR
R₂
┘
RR
BCR
1,R₂
BM
D₂(X₂,B₂)
┐
Branch if Mixed
RX
BC
4,D₂(X₂,B₂)
BMR
R₂
┘
RR
BCR
4,R₂
BZ
D₂(X₂,B₂)
┐
Branch if Zero
RX
BC
8,D₂(X₂,B₂)
BZR
R₂
┘
RR
BCR
8,R₂
BNO
D₂(X₂,B₂)
┐
Branch if Not Ones
RX
BC
14,D₂(X₂,B₂)
BNOR
R₂
┘
RR
BCR
14,R₂
BNM
D₂(X₂,B₂)
┐
Branch if Not Mixed
RX
BC
11,D₂(X₂,B₂)
BNMR
R₂
┘
RR
BCR
11,R₂
BNZ
D₂(X₂,B₂)
┐
Branch if Not Zero
RX
BC
7,D₂(X₂,B₂)
BNZR
R₂
┘
RR
BCR
7,R₂
Branch
Relative on
Condition Long
BRUL
label
Unconditional Br Rel Long
RIL
BRCL
15,label
BRHL
label
Br Rel Long on High
RIL
BRCL
2,label
BRLL
label
Br Rel Long on Low
RIL
BRCL
4,label
BREL
label
Br Rel Long on Equal
RIL
BRCL
8,label
BRNHL
label
Br Rel Long on Not High
RIL
BRCL
13,label
BRNLL
label
Br Rel Long on Not Low
RIL
BRCL
11,label
BRNEL
label
Br Rel Long on Not Equal
RIL
BRCL
7,label
BRPL
label
Br Rel Long on Plus
RIL
BRCL
2,label
BRML
label
Br Rel Long on Minus
RIL
BRCL
4,label
BRZL
label
Br Rel Long on Zero
RIL
BRCL
8,label
BROL
label
Br Rel Long on Overflow
RIL
BRCL
1,label
BRNPL
label
Br Rel Long on Not Plus
RIL
BRCL
13,label
BRNML
label
Br Rel Long on Not Minus
RIL
BRCL
11,label
BRNZL
label
Br Rel Long on Not Zero
RIL
BRCL
7,label
BRNOL
label
Br Rel Long on Not Overflow
RIL
BRCL
14,label
Figure 18. Extended mnemonic codes (part 3 of 5)
Chapter 4. Machine instruction statements
79
Branch Relative on Condition
BRO
label
Branch on Overflow
RI
BRC
1,label
BRP
label
Branch on Plus
RI
BRC
2,label
BRH
label
Branch on High
RI
BRC
2,label
BRL
label
Branch on Low
RI
BRC
4,label
BRM
label
Branch on Minus
RI
BRC
4,label
BRNE
label
Branch on Not Equal
RI
BRC
7,label
BRNZ
label
Branch on Not Minus
RI
BRC
7,label
BRE
label
Branch on Equal
RI
BRC
8,label
BRZ
label
Branch on Zero
RI
BRC
8,label
BRNL
label
Branch on Not Low
RI
BRC
11,label
BRNM
label
Branch on Not Minus
RI
BRC
11,label
BRNH
label
Branch on Not High
RI
BRC
13,label
BRNP
label
Branch on Not Plus
RI
BRC
13,label
BRNO
label
Branch on No Overflow
RI
BRC
14,label
BRU
label
Unconditional Branch
RI
BRC
15,label
Figure 19. Extended mnemonic codes (part 4 of 5)
Jump on Condition Long
JLU
label
Unconditional Jump Long
RIL
BRCL
15,label
JLNOP
label
No operation
RIL
BRCL
0,label
JLH
label
Jump Long on High
RIL
BRCL
2,label
JLL
label
Jump Long on Low
RIL
BRCL
4,label
JLE
label
Jump Long on Equal
RIL
BRCL
8,label
JLNH
label
Jump Long on Not High
RIL
BRCL
13,label
JLNL
label
Jump Long on Not Low
RIL
BRCL
11,label
JLNE
label
Jump Long on Not Equal
RIL
BRCL
7,label
JLP
label
Jump Long on Plus
RIL
BRCL
2,label
JLM
label
Jump Long on Minus
RIL
BRCL
4,label
JLZ
label
Jump Long on Zero
RIL
BRCL
8,label
JLO
label
Jump Long on Overflow
RIL
BRCL
1,label
JLNP
label
Jump Long on Not Plus
RIL
BRCL
13,label
JLNM
label
Jump Long on Not Minus
RIL
BRCL
11,label
JLNZ
label
Jump Long on Not Zero
RIL
BRCL
7,label
JLNO
label
Jump Long on Not Overflow
RIL
BRCL
14,label
Notes:
1. D₂=displacement, X₂=index register, B₂=base register, R₂=register containing branch address
2. The addresses represented are explicit address (see ▌4▐). However, implicit addresses can also be used in this type
of instruction.
|
3. You can use the Mixed condition mnemonics such as BM and BNM only after TEST UNDER MASK (TM or
|
TMY). Avoid using these mnemonics after any of the TEST UNDER MASK (HIGH/LOW) instructions (TMH,
|
TML, TMHH, TMHL, TMLH, or TMLL), as these instructions set the condition code for a mixture of ones and
|
zeros by treating the selected bits as a signed binary number, giving either the Minus or Plus result. You can
|
select these cases individually by using mnemonics for the Minus and Plus conditions, or combine them by using
|
a branch mask of 6 (for which there is no extended mnemonic) to select both cases.
Figure 20. Extended mnemonic codes (part 5 of 5)
Alternative mnemonics for some branch relative instructions
For some branch relative statements, there are alternative mnemonics. These are:
Table 9. Alternative mnemonics for some branch relative instructions
Instruction
Alternative
Description
BRAS
JAS
Branch Relative and Save
BRASL
JASL
Branch Relative and Save Long
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HLASM V1R6 Language Reference