x86 Assembly Language. Reference Manual (1995) - page 4

 

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x86 Assembly Language. Reference Manual (1995) - page 4

 

 

2
Description
bsr scans the bits, starting at the most significant bit, in the doubleword
operand or the second word. If the bits are all zero, ZF is cleared. Otherwise,
ZF is set and the bit index of the first set bit found, while scanning in the
reverse direction, is loaded into the destination register
Example
bsr 4(%edi), %edx
Bit Test (bt)
bt{wl} imm8, r/m[16|32]
bt{wl} reg[16|32], r/m[16|32]
Operation
BIT [LeftSRC, RightSRC]
CF
Description
The bit indicated by the first operand (base) and the second operand (offset)
are saved by bt into CF (carry flag).
Example
btl $253, 4(%edi)
btl %edx, 4(%edi)
Instruction-Set Mapping
101
2
Bit Test And Complement (btc)
btc{wl} imm8, r/m[16|32]
btc{wl} reg[16|32], r/m[16|32]
Operation
BIT [LeftSRC, RightSRC]
CF
NOT BIT [LeftSRC, RightSRC] BIT[LeftSRC, RightSRC]
Description
The bit indicated by the first operand (base) and the second operand (offset)
are saved by btc into CF (carry flag) and complements the bit.
Example
btl $253, 4(%edi)
btl %edx, 4(%edi)
Bit Test And Reset (btr)
btr{wl} imm8, r/m[16|32]
btr{wl} reg[16|32], r/m[16|32]
Operation
BIT[LeftSRC, RightSRC]
CF
0 BIT[LeftSRC, RightSRC]
Description
The value of the first operand (base) and the second operand (bit offset) are
saved by btr into the carry flag and then it stores 0 in the bit.
Example
btrl $253, 4(%edi)
btrl $edx, 4(%edi)
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2
Bit Test And Set (bts)
bts{wl}
imm8, r/m[16|32]
bts{wl}
reg[16|32], r/m[16|32]
Operation
BIT[LeftSRC, RightSRC]
CF
0 BIT[LeftSRC, RightSRC]
Description
The value of the first operand (base) and the second operand (bit offset) are
saved by bts into the carry flag and then it stores 1 in the bit.
Example
btsl $253, 4(%edi)
btsl $edx, 4(%edi)
Exchange Instructions
Compare and Exchange (cmpxchg)[486]
cmpxchg{bwl}reg[8|16|32], r/m[8|16|32]
Example
cmpxchgb %cl, 1(%esi)
cmpxchgl %edx, 4(%edi)
Instruction-Set Mapping
103
2
Floating-Point Transcendental Instructions
Floating-Point Sine (fsin)
fsin
Example
Replace the contents of the top of the stack with its sine.
fsin
Floating-Point Cosine (fcos)
fcos
Example
Replace the contents of the top of the stack with its cos.
fcos
Floating-Point Sine and Cosine (fsincos)
fsincos
Example
Replace the contents of the top of the stack with its sine and then push the
cosine onto the FPU stack.
fsincos
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Floating-Point Constant Instructions
Floating-Point Load One (fld)
fld1
fld12+
fld12e
fldpi
fldlg2
fldln2
fldz
Example
Use these constant instructions to push often-used values onto the FPU
stack.
fldl 2(%ecx)
Processor Control Floating-Point Instructions
Floating-Point Load Control Word (fldcw)
fldcwr/m16
Example
Load the FPU control word with the value in the specified memory address.
fldcw 2(%ecx)
Instruction-Set Mapping
105
2
Floating-Point Load Environment (fldenv)
fldenvmem
Example
Reload the FPU environment from the source-operand specified memory
space.
fldenv 2(%ecx)
Miscellaneous Floating-Point Instructions
Floating-Point Different Reminder (fprem)
fprem1
Example
Divide stack element 0 by stack element 1 and leave the remainder in stack
element 0.
fprem
Floating-Point Comparison Instructions
Floating-Point Unsigned Compare (fucom)
fucomfreg
Description:
Compare stack element 0 with stack element (i). Use condition codes:
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No compare: 111
(i) < stack 0:
000
(i) > stack 0:
001
(i) = stack 0:
100
Example
Compare stack element 0 with stack element 7.
fucom %st(7)
Floating-Point Unsigned Compare And Pop (fucomp)
fucompfreg
Description
Compare stack element 0 with stack element (i). Use condition codes shown for
fucom. Then pop the stack.
Example
fucomp %st(7)
Floating-Point Unsigned Compare And Pop Two (fucompp)
fucompp
Description
Compare stack element 0 with stack element (i). Use condition codes shown for
fucom. Then pop the stack twice.
Instruction-Set Mapping
107
2
Example
fucompp %st(7)
Load and Move Instructions
Load Effective Address (lea)
lea{wl} r/m[16|32], reg[16|32]
Operation
Addr(m) r16
Addr(m) r32
Truncate to 16 bits(Addr(m)) r16
Truncate to 16 bits(Addr(m)) r32
Description
The offset part of the effective address is calculated by lea and stored in the
specified register. The specified register determines the operand-size
attribute if the instruction. The USE attribute of the segment containing the
second operand determines the address-size attribute.
Example
leal 0x33333333, %edx
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Move (mov)
mov{bwl}imm[8|16|32], r/m[8|16|32]
mov{bwl}reg[8|16|32], r/m[8|16|32]
mov{bwl}r/m[8|16|32], reg[8|16|32]
Operation
SRC DEST
Description
mov stores or loads the following special registers in or from a general
purpose register.
Control registers CR0, CR2, and CR3
Debug registers DR0, DR1, DR2, DR3, DR6, and DR7
Test registers TR6 and TR7
These instructions always use 32-bit operands.
Example
movl %cr3, %ebp
movl %db7, %ebp
movl %ebp, %cr3
movl %ebp, %db7
movl %tr7, %ebp
movl %ebp, %tr7
Move Segment Registers (movw)
movwsreg,r/m16
movwr/m16, sreg
Operation
r/m16 Sreg
Sreg r/m16
Instruction-Set Mapping
109
2
Description
movw copies the first operand to the second operand, including data from a
descriptor. The descriptor table entry for the selector contains the data for
the register. The DS and ES registers can be loaded with a null selector
without causing an exception. Use of DS or ES however, causes a #GP(0),
and no memory reference occurs.
All interrupts are inhibited until after the execution of the next instruction,
after a movw into SS. Special actions and checks result from loading a
segment register under Protected Mode.
Example
movw %CS, 5(%ebx)
movw %(%ebx), %CS
Move Control Registers (mov)
mov{l}creg, reg32
mov{l}reg32, creg
Operation
SRC DEST
Description
This form of mov stores or loads the Control Register CR0, CR2, or CR4 to
or from a general purpose register.
These instructions are always used with 32-bit operands.
Example
movl %cr3, %ebp
movl %ebp, %cr3
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Move Debug Registers (mov)
mov{l}dreg, reg32
mov{l}reg32, dreg
Operation
SRC DEST
Description
This form of mov stores or loads the Debug Register DR1, DR2, or DR3, DR6,
and DR7 to or from a general purpose register.
These instructions are always used with 32-bit operands.
Example
movl %db7, %ebp
movl %ebp, %db7
Move Test Registers (mov)
mov{l}treg, reg32
mov{l}reg32, treg
Operation
SRC DEST
Description
This form of mov stores or loads the Test Register TR6 or TR7 to or from a
general purpose register.
These instructions are always used with 32-bit operands.
Instruction-Set Mapping
111
2
Example
movl %tr7, %ebp
movl %ebp, %tr7
Move With Sign Extend (movsx)
movsx{wl}r/m8, reg[16|32]
movsxwl r/m16, reg32
Operation
SignExtend(SRC) DEST
Description
movsx reads the contents of the register or effective address as a word or
byte. movsx then sign-extends the 16- or 32-bit value to the operand-size
attribute of the instruction. The result is stored in the destination register by
movsx.
Example
movsxbl 1(%esi), %edx
movsxwl 5(%ebx), %edx
Move With Zero Extend (movzb)
movzb[wl]r/m8, reg[16|32]
movzwl r/m16, reg32
Operation
SignExtend(SRC) DEST
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Description
movzx reads the contents of the register or effective address as a word or
byte. movzx then sign-extends the 16- or 32-bit value to the operand-size
attribute of the instruction. The result is stored in the destination register by
movzx.
Example
Pop Instructions
Pop All General Registers (popa)
popa{wl}
Operation
POP r16
POP r32
Description
The eight 16-bit general registers are popped by popa. However, the SP
value is not loaded into SP, It is discarded. popa restores the general
registers to their values before a previous pusha was executed. DI is the
first register popped.
The eight 32-bit registers are popped by popad. However, the ESP value is
not loaded into ESP, it is discarded. popad restores the general registers to
their values before a previous pushad was executed. EDI is the first register
popped.
Example
popal
Instruction-Set Mapping
113
2
Push Instructions
Push All General Registers (pusha)
pusha{wl}
Operation
SP r16
SP r32
Description
The 16-bit or 32-bit general registers are saved by pusha and pushad,
respectively. The stack pointer is decremented by 16 by pusha to hold the
eight word values. The stack pointer is decremented by 32 by pushad to
hold the eight doubleword values. The registers are pushed onto the stack in
the order received; the stack bytes appear in reverse order. DI or EDI is the
last stack pushed.
Example
pushal
Rotate Instructions
Rotate With Carry Left (rcl)
rcl{bwl}imm8, r/m[8|16|32]
rcl{bwl}%cl, r/m[8|16|32]
Operation
r/m high-order bit CF
CF r/m low-order bit
r/m ShiftLeft
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Description
The left rotate instruction shifts all bits in the register or memory operand
specified. The carry flag (CF) is included in the rotation. The most
significant bit is rotated to the carry flag, the carry flag is rotated to the least
significant bit position, all other bits are shifted to the left. The result
includes the original value of the carry flag.
The first operand value indicates how many times the rotate takes place.
The value is either the contents of the CL register or an immediate number.
For a single rotate, where the first operand is one, the overflow flag (OF) is
defined. For all other cases, OF is undefined. After the shift, the carry flag
bit is XORed with the most significant result bit.
Example
rclb $1, 1(%esi)
rclb $253, 1(%esi)
rclb %cl, 1(%esi)
rcll $1, 4(%edi)
rcll $253, 4(%edi)
rcll %cl, 4(%edi)
Rotate With Carry Right (rcr)
rcr{bwl}imm8, r/m[8|16|32]
rcr{bwl}%cl, r/m[8|16|32]
Operation
r/m high-order bit CF
CF r/m low-order bit
r/m ShiftRight
Description
The right rotate instruction shifts all bits in the register or memory operand
specified. The carry flag (CF) is included in the rotation. The least significant
bit is rotated to the carry flag, the carry flag is rotated to the most significant
bit position, all other bits are shifted to the right. The result includes the
Instruction-Set Mapping
115
2
original value of the carry flag.
The first operand value indicates how many times the rotate takes place.
The value is either the contents of the CL register or an immediate number.
For a single rotate, where the first operand is one, the overflow flag (OF) is
defined. For all other cases, OF is undefined. After the shift, the carry flag
bit is XORed with the two most significant result bits.
Example
rcrb $1, 1(%esi)
rcrb $253, 1(%esi)
rcrb %cl, 1(%esi)
rcrl $1, 4(%edi)
rcrl $253, 4(%edi)
rcrl %cl, 4(%edi)
Rotate Left (rol)
rol{bwl}imm8, r/m[8|16|32]
rol{bwl}%cl, r/m[8|16|32]
Operation
r/m high-order bit CF
CF r/m low-order bit
r/m ShiftLeft
Description
The left rotate instruction shifts all bits in the register or memory operand
specified. The most significant bit is rotated to the carry flag, the carry flag is
rotated to the least significant bit position, all other bits are shifted to the
left. The result does not include the original value of the carry flag.
The first operand value indicates how many times the rotate takes place.
The value is either the contents of the CL register or an immediate number.
For a single rotate, where the first operand is one, the overflow flag (OF) is
defined. For all other cases, OF is undefined. After the shift, the carry flag
bit is XORed with the most significant result bit.
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Example
rclb $1, 1(%esi)
rclb $253, 1(%esi)
rclb %cl, 1(%esi)
rcll $1, 4(%edi)
rcll $253, 4(%edi)
rcll %cl, 4(%edi)
Rotate Right (ror)
ror{bwl}imm8, r/m[8|16|32]
ror{bwl}%cl, r/m[8|16|32]
Operation
r/m high-order bit CF
CF r/m low-order bit
r/m ShiftRight
Description
The right rotate instruction shifts all bits in the register or memory operand
specified. The least significant bit is rotated to the carry flag, the carry flag is
rotated to the most significant bit position, all other bits are shifted to the
right. The result does not include the original value of the carry flag.
The first operand value indicates how many times the rotate takes place.
The value is either the contents of the CL register or an immediate number.
For a single rotate, where the first operand is one, the overflow flag (OF) is
defined. For all other cases, OF is undefined. After the shift, the carry flag
bit is XORed with the two most significant result bits.
Instruction-Set Mapping
117
2
Example
rcrb $1, 1(%esi)
rcrb $253, 1(%esi)
rcrb %cl, 1(%esi)
rcrl $1, 4(%edi)
rcrl $253, 4(%edi)
rcrl %cl, 4(%edi)
Byte Instructions
Byte Set On Condition (setcc)
setcc r/m8
Operation
ConditionTrue: 1 r/m8
ConditionFalse: 0 rm/8
Description
If the condition is met, setcc stores a one byte at the destination specified
by the effective address. If the condition is not met, setcc stores a zero
byte. Table 2-10 on page 119 lists the setcc condition options. Similar
condition options are separated by commas, followed by the flag condition.
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Table 2-10 setcc Condition List
Instruction (set+cc)
Set Byte If:
seta, setnbe
greater, not equal or less than, CF=0 & ZF=0
setae, setnc, setnb
equal or greater, not carry, not less than, CF=0
setb, setc, setnae
less than carry, carry = 1, not equal or greater than, CF=1
setbe, setna
equal or less than, not greater than carry, CF=1 or ZF=1
sete, setz
equal, zero, ZF=1
setg, setnle
greater, ZF=0 or SF=OF. not equal or less, ZF=1 or SF OF
setge, setnl
equal or greater, not less, SF = OF
setl, setnge
less, not equal or greater, SF OF
setle, setng
equal or less, not greater, ZF = 1 and SF OF
setne, setnz
not equal, not zero, ZF = 0
setno
not overflow, OF = 0
setns
not sign, SF=0
seto
overflow, OF = 1
setpe, setp
parity even, parity, PF = 1
setpo, setnp
parity odd, not parity, PF = 0
sets
sign, SF = 1
Example
set(cc) 1(%esi)
Instruction-Set Mapping
119
2
Byte Swap (bswap) [486]
bswapreg[16|32]
Example
Convert little/big endian to big/little endian by swapping bytes.
bswap %ebx
Exchange Instructions
Exchange And Add (xadd) [486]
xadd{bwl}reg[8|16|32], r/m[8|16|32]
Example
Exchange the byte contents of the ESI register with the byte register and
load the sum into the ESI register.
xaddb %cl, 1(%esi)
Exchange Register / Memory With Register (xchg)
xchg{bwl}reg[8|16|32], r/m[8|16|32]
Operation
DEST temp
SRC DEST
temp SRC
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Description
Two operands, in either order, are exchanged by xchg. During the exchange,
BUS LOCK is asserted (regardless of the value of IOPL or the LOCK prefix)
if a memory operand is part of the exchange.
Example
xchgb %cl, 1(%esi)
/*exchange byte register with EA byte */
xchgl %ebp, %eax
xchgl %ebx, %eax
xchgl %ecx, %eax
xchgl %edi, %eax
xchgl %edx, %eax
xchgl %edx, 4(%edi)
/*exchange word register with EA word */
xchgl %esi, %eax
xchgl %esp, %eax
Miscellaneous Instructions
Write Back and Invalidate Cache (wbinvd) [486 only]
wbinvd
Example
Write back and invalidate the cache.
wbinvd
Instruction-Set Mapping
121
2
Invalidate (invd) [486 only]
invd
Example
Invalidate the entire cache.
invd
Invalidate Page (invlpg) [486 only]
invlpgmem32
Example
Invalidate a single entry in the translation lookaside buffer.
invlpg 5(%ebx)
LOCK Prefix (lock)
lock
Operation
LOCK# NEXT Instruction
Description
The LOCK # signal is asserted during execution of the instruction following
the lock prefix. This signal can be used in a multiprocessor system to
ensure exclusive use of shared memory while LOCK # is asserted. The bts
instruction is the read-modify-write sequence used to implement test-and-
run.
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The lock prefix works only with the instructions listed here. If a lock
prefix is used with any other instructions, an undefined opcode trap is
generated.
bt, bts, btr, btc
m, r/imm
xchg
r, m
xchg
m, r
add, or, adc, sbb, and, sub, xor
m, r/imm
not, neg, inc, dec
m
Memory field alignment does not affect the integrity of lock.
If a different 80386 processor is concurrently executing an instruction that
has a characteristic listed here, locked access is not guaranteed. The
previous instruction:
Does not follow a lock prefix
Is not on the previous list of acceptable instructions
A memory operand specified has a partial overlap with the destination
operand.
Example
lock
No Operation (nop)
nop
Operation
NO OPERATION
Description
No operations are performed by nop. The xchgl %eax, %eax instruction is
an alias for the nop instruction.
Instruction-Set Mapping
123
2
Example
nop
Halt (hlt)
hlt
Address Prefix
addr16
Data Prefix
data16
Operation
HLT ENTER HALT STATE
Description
halt puts the 80386 in a HALT state by stopping instruction execution.
Execution is resumed by an nmi or an enabled interrupt. After a halt, if an
interrupt is used to continue execution, the saved CS:EIP or CS:IP value
points to the next instruction (after the halt).
The halt instruction is privileged.
Example
hlt
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Real Transfer Instructions
Load Real (fld)
fld{lst}
Operation
SRC STACK ELEMENT 0
Description
The source operand is pushed onto the stack by fld. The register used
before the stack top-pointer is decremented, is the register number used if
the source is a register.
Example
Load stack element 7 onto stack element 0.
fld %st (7)
Store Real (fst)
fst{ls}
Operation
STACK ELEMENT 0 DESTINATION
Description
The current value of stack element 0 is copied to the destination. The
destination can be a single- or double-real memory operand or another
register.
Instruction-Set Mapping
125
2
Example
Store the contents of stack element 7 onto stack element 0.
%fst (7)
Store Real and Pop (fstp)
fstp{lst}
Operation
STACK ELEMENT 0 DESTINATION THEN POP
Description
The current value of stack element 0 is copied to the destination. The
destination can be a single-, double-, or extended-real memory operand, or
another register. Then pop the stack register.
Example
Copy the contents of stack element 0 onto stack element 7 and pop stack
element 0.
%fstp (7)
Exchange Registers (fxch)
fxch
Example
Exchange the contents of stack element 0 and stack element 7.
fxch %st(7)
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Integer Transfer Instructions
Integer Load (fild)
fild{l|ll}
Example
Convert the integer operand (signed) into extended-real and load it onto the
floating-point stack.
fild 2(%eax)
Integer Store (fist)
fist{l}
Example
Convert the value in stack element 0 into a signed integer and transfer the
result to register ECX with an offset of 2.
fist 2(%ecx)
Integer Store and Pop (fistp)
fistp{l|ll}
Example
Convert the value in stack element 0 into a signed integer and transfer the
result to register ECX with an offset of 2, then pop the stack.
fistp 2(%ecx)
Instruction-Set Mapping
127
2
Packed Decimal Transfer Instructions
Packed Decimal (BCD) Load (fbld)
fbld
Example
Convert the source operand (BCD) into extended-real and push it onto the
floating-point stack.
fbld 2(%ecx)
Packed Decimal (BCD) Store and Pop (fbstp)
fbstp
Example
Convert the value in stack element 0 to a packed decimal integer and store
the result in register ECX with an offset of 2, and pop the stack.
fbstp 2(%ecx)
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Addition Instructions
Real Add (fadd)
fadd{ls}
Example
Add stack element 7 to stack element 0 and return the sum to stack element
0.
fadd %st(7), %st
Real Add and Pop (faddp)
faddp
Example
Add stack element 0 to stack element 7 and return the sum to stack element
7, then pop the stack.
faddp %st, %st(7)
Integer Add (fiadd)
fiadd{l}
Example
Add the integer contents of register ECX to stack element 0.
fiadd 2(%ecx)
Instruction-Set Mapping
129
2
Subtraction Instructions
Subtract Real and Pop (fsub)
fsub{ls}
Example
Subtract stack element 7 from stack element 0 and return the difference to
stack element 0.
fsub %st(7), %st
Subtract Real (fsubp)
fsubp
Example
Subtract stack element 7 from stack element 0 and return the difference to
stack element 7, then pop the stack.
fsubp %st, %st(7)
Subtract Real Reversed (fsubr)
fsubr{ls}
Example
Subtract stack element 0 from stack element 7 and return the difference to
stack element 0.
fsubr %st(7), %st
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Subtract Real Reversed and Pop (fsubrp)
fsubrp
Example
Subtract stack element 0 from stack element 7 and return the difference to
stack element 7, then pop the stack.
fsubrp %st, %st(7)
Integer Subtract (fisubrp)
fisubrp
Example
Subtract stack element 0 from the integer contents of register ECX (with an
offset of 2) and return the difference to register ECX, then pop the stack.
fisubrp 2(%ecx)
Integer Subtract Reverse (fisubr)
fisubr{l}
Example
Subtract stack element 0 from the integer contents of register ECX (with an
offset of 2) and return the difference to stack element 0.
fisubr 2(%ecx)
Instruction-Set Mapping
131
2
Multiplication Instructions
Multiply Real (fmul)
fmul{ls}
Example
Multiply stack element 7 by stack element 0 and return the product to stack
element 0.
fmul %st(7), %st
Multiply Real and Pop (fmulp)
fmulp
Example
Multiply stack element 0 by stack element 7 and return the product to stack
element 7, then pop the stack.
fmulp %st, %st(7)
Integer Multiply (fimul)
fimul{l}
Example
Multiply the integer contents of register ECX by stack element 0, return the
product to register ECX.
fimul 2(%ecx)
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Division Instructions
Divide Real (fdiv)
fdiv{ls}
Example
Divide stack element 0 by stack element 7 and return the result to stack
element 0.
fdiv %st(7), %st
Divide Real and Pop (fdivp)
fdivp
Example
Divide stack element 7 by stack element 0 and return the result to stack
element 7, then pop the stack.
fdivp %st, %st(7)
Divide Real Reversed (fdivr)
fdivr{ls}
Example
Divide stack element 0 by stack element 7 and return the result to stack
element 7.
fdivr %st, %st(7)
Instruction-Set Mapping
133
2
Divide Real Reversed and Pop (fdivrp)
fdivrp
Example
Divide stack element 0 by stack element 7 and return the result to stack
element 7, then pop the stack.
fdivrp %st, %st(7)
Integer Divide (fidiv)
fidiv{l}
Example
Divide stack element 0 by the integer contents of register ECX, with an
offset of 2, and return the result to register ECX.
fidiv 2(%ecx)
Integer Divide Reversed (fidivr)
fidivr{l}
Example
Divide the integer contents of register ECX, with an offset of 2, by stack
element 0 and return the result to stack element 0.
fidivr 2(%ecx)
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Floating-Point Opcode Errors
Warning - The SunOS x86 assembler generates the wrong object code for some
of the floating-point opcodes fsub, fsubr, fdiv, and fdivr when there are
two floating register operands, and the second op destination is not the zeroth
floating-point register. This error has been made to many versions of the USL
UNIX® system and would probably cause problems if it were fixed.
Replace the following instructions, in column 1, with their substitutions, in
column 2, for x86 platforms:
Table 2-11
Floating-point Opcodes
fsub %st,%st(n)
fsubr %st, %st(n)
fsubp %st,%st(n)
fsubrp %st, %st(n)
fsub
fsubr
fsubr %st,%st(n)
fsub %st, %st(n)
fsubrp %st,%st(n)
fsubp %st, %st(n)
fsubr
fsub
fdiv %st,%st(n)
fdivr %st,%st(n)
fdivp %st,%st(n)
fdivrp %st,%st(n)
fdiv
fdivr
fdivr %st, %st(n)
fdvir %st, %st(n)
fdivrp %st, %st(n)
fdivp %st, %st(n)
fdivr
fdiv
Instruction-Set Mapping
135
2
Miscellaneous Arithmetic Operations
Square Root (fsqrt)
fsqrt
Example
Replace stack element 0 with the square root of its value.
fsqrt
Scale (fscale)
fscale
Example
Add the integer value in stack element 1 to the exponent of stack element 0
(multiplication and division by powers of 2).
fscale
Partial Remainder (fprem)
fprem
Example
Divide stack element 0 by stack element 1 and return the (partial) remainder
to stack element 0.
fprem
136
x86 Assembly Language Reference Manual—November 1995
2
Round to Integer (frndint)
frndint
Example
Round the value in stack element 0 to an integer according to the FPU
control word RC field.
frndint
Extract Exponent and Significand (fxtract)
fxtract
Example
Separate stack element 0 into its exponent and significand and return the
exponent to stack element 0, then push the significand onto the FPU stack.
fxtract
Absolute Value (fabs)
fabs
Example
Replace stack element 0 with its absolute value.
fabs
Instruction-Set Mapping
137
2
Change Sign (fchs)
fchs
Example
Replace the sign of stack element 0 with the opposite sign.
fchs
Comparison Instructions
Compare Real (fcom)
fcom{ls}
Example
Compare stack element 0 with stack element 7. Condition codes contain the
result: No compare=111, st 0 greater than st 7=000, st 0 less than st 7=001,
equal compare=100.
fcom %st(7)
138
x86 Assembly Language Reference Manual—November 1995
2
Compare Real and Pop (fcomp)
fcomp{ls}
Example
Compare stack element 0 with stack element 7. Condition codes contain the
result: No compare=111, st 0 greater than st 7=000, st 0 less than st 7=001,
equal compare=100, then pop the stack.
fcomp %st(7)
Compare Real and Pop Twice (fcompp)
fcompp
Example
Compare stack element 0 with stack element 1. Condition codes contain the
result: No compare=111, st 0 greater than st 7=000, st 0 less than st 7=001,
equal compare=100, then pop the stack twice.
fcompp
Integer Compare (ficom)
ficom{l}
Example
Integer compare stack element 0 with the contents of register ECX (with an
offset of 2). Condition codes contain the result: No compare=111, st 0 greater
than st 7=000, st 0 less than st 7=001, equal compare=100,
ficom 2(%ecx)
Instruction-Set Mapping
139
2
Integer Compare and Pop (ficomp)
ficomp{l}
Example
Integer compare stack element 0 with the contents of register ECX (with an
offset of 2). Condition codes contain the result: No compare=111, st 0 greater
than st 7=000, st 0 less than st 7=001, equal compare=100, then pop the
stack.
ficomp 2(%ecx)
Test (ftst)
ftst
Example
Compare stack element 0 with the value 0.0. Condition codes contain the
result: No compare=111, st 0 greater than st 7=000, st 0 less than st 7=001,
equal compare=100,
ftst
Examine (fxam)
fxam
Example
Report the type of object in stack element 0. FPU flags C3, C2, and C0 return
the type:
140
x86 Assembly Language Reference Manual—November 1995

 

 

 

 

 

 

 

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